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JESD204B IP Core Stratix V Interoperability Reference Design with AD9680

JESD204B IP Core Stratix V Interoperability Reference Design with AD9680

Last Major Update

Second Release - Dec 19th 2014- Quartus II v14.1 Installed

First Release - Nov 11th 2014 - Quartus II v14.0 Installed


Design Overview

This reference design demonstrates the implementation of JESD204B IP Core in Stratix® V GX interoperates with AD9680 converter from Analog Devices Inc. (ADI). This design contains one JESD204B duplex IP core and other components that are identical to the components in AN710. Refer to Figure 2 System Diagram of AN710. In this reference design, where LMF = 421, S=1, K=32 and descrambler is on, the data rate of transceiver lanes is 12.5 Gbps. External clock sources provides 1.25GHz device clock to the ADC and 312.5MHz device clock to FPGA. Both device clocks are synchronous and no phase shift to each other. 

A graphical user interface (GUI) that runs on system console, called the JESD204B IP Toolkit is included in this reference design that is compiled with Quartus II v14.1 and beyond. The command line system console scripts, main.tcl and the supporting TCL scripts are located in cmd_line_scripts folder is an alternative to run this reference design if you do not want to use the JESD204B IP Toolkit. 

Below are the customized components for this reference design:

  • A QSYS based control unit that provides reset sequence for the IP core. This reset sequence is dictated by the reset procedure in main.tcl if you are using the command line system console; if using the JESD204B IP Toolkit, this reset sequence is dictated by the RESET procedure in jesd204b_ip_inc.tcl. IP core configuration can be implemented in this reset or RESET procedure, before the link reset is de-asserted. In this example, SYSREF detection mode is set to continuous mode; the test mode is set to PRBS test pattern. The control unit also gathers IP core interrupt and pattern checker status, enable/disable internal serial loopback for duplex IP core. It has a 4-wire SPI master interface to configure the converter.
  • The SYSREF generator in FPGA generates continuous SYSREF pulses to both the ADC and JESD204B IP core. The SYSREF pulses frequency is 1*LMFC = (FPGA link clock * 4)/(F*K) = 1250/32 = 39.0625 MHz.

Note: Before you start testing this reference design on the hardware, install 0 ohm resistors or make solder bridges at location R814 and

R815 at the AD9680 EVM. This rework routes SYSREF pulses from FPGA to ADC.

Note: For convenient hardware setup, the SYSREF is generated by FPGA. However, the common practice in JESD204B application is to source

SYSREF from the clock source that provides device clock to the subsystem.


System Diagram SV_AD9680_ref_design_blk_diagram.jpg


AD9680 EVM Ad9680evb2.jpg


Hardware Requirements


Software Requirements

  • Quartus II 14.1 or later with JESD204B IP Core installed


Running the Design

1. Download the design file in the link below.

2. Set up the hardware by connecting AD9680 EVM into the FMC port of Stratix V Advanced Systems Development Board. Refer to Figure 1 Hardware Setup of AN710.

Note: The latest version of AD9680 EVM (AD9680-1000EBZ) from ADI looks different than the EVM used in AN710.

3. Connect 1.25GHz ADC device clock source to J801 (Sample Clock) on AD9680 EVM using SMA cable.

4. Connect 312.5MHz FPGA device clock source to J804 (Ref Clock) on AD9680 EVM using SMA cable

5. Turn on the device clock for both ADC and FPGA before powering up the development kit.

6. Launch SignalTap and configure the first FPGA in JTAG chain with /output_files/svgx_jesd204b_ad9680_ed_14_1.sof. in svgx_jesd204b_ad9680_ed_14.1.qar

7. In SignalTap, at the rx_link instance, click Run Analysis icon below the menu bar.

8. If you are using the JESD204B IP toolkit, execute the following steps. If you are using command line system console script, skip step 8 and go to step 9.

a. Launch system console and type source main_gui.tcl in the system console window. The GUI takes ~1 minute to be fully loaded into system console window.

b. After the GUI is fully loaded, click Configure Converter button at the top row of the Main Control tab.

c. Select Continuous SYSREF Detection from the RX : drown-down list box at the Step 3: IP Core Configuration section.

d. Select PRBS from the drop down list of Pattern Checker Mode in RX section.

Note: You can view a demonstration video clip for using the JESD204B IP Toolkit on this reference design at http://youtu.be/ZqGmaLqQxvU

Exit the system console if you want to re-configure the FPGA.

9. If you are using command line system console script, execute the following steps. If you are using IP Toolkit GUI, skip step 9 and go to step 10.

a. Launch system console and type cd cmd_line_scripts in the system console window.

b. Type source main.tcl, then type these commands in sequence:

config_spi_slave

reset

Note: For v14.0 reference design, you need to type output_sysref 1 after config_spi_slave command.

10. The SignalTap is triggered when rising edge of rx_dev_sync_n is detected. The JESD204B link enters user data phase when dev_lane_aligned signal is asserted.

11. ADC test pattern generator transmits short PRBS test pattern. The test pattern can be observed at jesd204_rx_dataout bus at rx_trpt instance in SignalTap.

Note: For normal operation between ADC and FPGA, the continuous SYSREF pulses must be turned on even after the link is up.

Additional information

You can run this reference design in internal serial loopback mode by typing sloopback 1 in the system console window.

System console commands:

Command NameArgumentDescription
config_spi_slaveNot applicableConfigure converter through SPI programming interfaces.
resetNot applicableGlobal reset. It sequences the reset for JESD204B IP core and other components in the reference design. JESD204B IP core configuration prior to de-assertion of link reset can be executed in this procedure.
output_sysref0-1Output SYSREF pulses.

0: Disable (default)
1: Enable

sloopback0-1Internal serial loopback.

0: Disable (default)
1: Enable

set_scr0-1Set JESD204B IP core descrambler bit in ilas_data1 register

0: Disable
1: Enable

read_statusNot applicableRead the status of pattern checker's error signal, JESD204B IP core's interrupt signals and core PLL's locked signal.
read_rxstatus0-7Read JESD204B IP core rx_status<0..7> register (read back data in hexadecimal number).

For example, read_rxstatus 0 reads the content of rx_status0 register.

read_rx_ilas_data1, 2Read JESD204B IP core ilas_data<1,2> register (read back data in hexadecimal number).

For example, read_rx_ilas_data 1 reads the content of ilas_data1 register.

read_rx_err0, 1Read JESD204 rx_err<0..1> register (read back data in hexadecimal number) and display the error message if any. Error status in the entire RX IP core.
read_rbd_countNot applicableRead RBD value from rx status 0 register (read back value in decimal number).
read_rx_sysref_statusNot applicableRead SYSREF detection status for SYSREF Single Detection mode.
reinit_rxNot applicableReinitialize RX link by setting bit 1 of syncn_sysref_ctrl register. This bit will automatically be cleared once link reinitialization is completed.
set_testmodeoff, k28.5, d21.5, alt, ramp, prbsSelect transport layer and link layer test mode through rx_test and tx_test registers of JESD204B IP core.

off: Normal operation

Link layer test mode:
k28.5: A continuous sequence of /K28.5/ characters. For internal serial loopback only.
d21.5: A continuous sequence of /D21.5/ characters. For internal serial loopback only.

Transport layer test mode:
alt: Alternate checkerboard test pattern at pattern generator/checker.
ramp: Ramp test pattern at pattern generator/checker.
prbs: PRBS test pattern at pattern generator/checker. The POLYNOMIAL_LENGTH and FEEDBACK_TAP parameters are set at the parameter declaration section of jesd204b_ed.sv.


Link to the Design Files

Download [svgx_jesd204b_ad9680_ed_14.1.qar ]

Archive [svgx_jesd204b_ad9680_ed_14.0.qar ]

History

Initial release - 11 Nov 2014

Includes JESD204B IP Toolkit in v14.1 reference design. Set LVDS IO standard setting for sysref_out signal. Update jesd204b_ed.sv and main.tcl. (2014-12-19 welho)


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