First Release - Oct 27th 2014 - Quartus II v14.0 Installed
This reference design demonstrates the implementation of JESD204B IP Core in Stratix® V GX interoperates with AD9625 converter from Analog Devices Inc. (ADI). This design contains one JESD204B duplex IP core and other components that are identical to the components in AN712. Refer to Figure 2 System Diagram of AN712. In this reference design, where LMF = 811 (generic 8 lane mode on ADC), S=4, K=32 and descrambler is on, the data rate of transceiver lanes is 6.25 Gbps. The oscillator on AD9625 EVM provides 2.5GHz device clock to the ADC; ADC divides this clock by 4 and supplies 625MHz device clock to FPGA.
Below are the customized components for this reference design:
Note: If SYSREF is provided by external clock source that supplies the device clock to ADC, the rework instruction is available from AD9625 EVM web link below. Due to this
reason and a more convenient hardware setup, the SYSREF is generated by FPGA. However, the common practice in JESD204B application is to source SYSREF from the clock
source that provides device clock to the subsystem.
System Diagram- SV_AD9625_ref_design_blk_diagram.jpg (Click here for image)
1. Download the design file in the link below.
2. Set up the hardware by connecting AD9625 EVM into the FMC port of Stratix V Advanced Systems Development Board. Refer to Figure 1 Hardware Setup of AN712.
Note: The latest version of AD9625 EVM (AD-FMCADC2-EBZ FMC) from ADI has a 2.5GHz on-board oscillator. Hence, external clock source is not needed.
The setup in AN712 requires external clock source because the older version of AD9625 EVM doesn't have on-board oscillator.
3. Launch SignalTap and configure the first FPGA in JTAG chain with /output_files/svgx_jesd204b_ad9625_ed_14_0.sof. in svgx_jesd204b_ad9625_ed_14.0.qar
4. In SignalTap, at the rx_link instance, click Run Analysis icon below the menu bar.
5. Launch system console and type source main.tcl in the system console window. Then type these commands in sequence:
6. The SignalTap is triggered when rising edge of rx_dev_sync_n is detected. The JESD204B link enters user data phase when dev_lane_aligned signal is asserted.
7. ADC test pattern generator transmits ramp test pattern. The test pattern can be observed at jesd204_rx_dataout bus at rx_trpt instance in SignalTap.
8. After the JESD204B link is up, optionally you can turn off the SYSREF pulses by typing output_sysref 0 command in system console window.
You can run this reference design in internal serial loopback mode by typing sloopback 1 in the system console window.
System console commands:
|config_spi_slave||Not applicable||Configure converter through SPI programming interfaces.|
|reset||Not applicable||Global reset. It sequences the reset for JESD204B IP core and other components in the reference design. JESD204B IP core configuration prior to de-assertion of link reset can be executed in this procedure.|
|output_sysref||0-1||Output SYSREF pulses.|
0: Disable (default)
|sloopback||0-1||Internal serial loopback.|
0: Disable (default)
|set_scr||0-1||Set JESD204B IP core descrambler bit in ilas_data1 register|
|read_status||Not applicable||Read the status of pattern checker's error signal, JESD204B IP core's interrupt signals and core PLL's locked signal.|
|read_rxstatus||0-7||Read JESD204B IP core rx_status<0..7> register (read back data in hexadecimal number).|
For example, read_rxstatus 0 reads the content of rx_status0 register.
|read_rx_ilas_data||1, 2||Read JESD204B IP core ilas_data<1,2> register (read back data in hexadecimal number).|
For example, read_rx_ilas_data 1 reads the content of ilas_data1 register.
|read_rx_err||0, 1||Read JESD204 rx_err<0..1> register (read back data in hexadecimal number) and display the error message if any. Error status in the entire RX IP core.|
|read_rbd_count||Not applicable||Read RBD value from rx status 0 register (read back value in decimal number).|
|read_rx_sysref_status||Not applicable||Read SYSREF detection status for SYSREF Single Detection mode.|
|reinit_rx||Not applicable||Reinitialize RX link by setting bit 1 of syncn_sysref_ctrl register. This bit will automatically be cleared once link reinitialization is completed.|
|set_testmode||off, k28.5, d21.5, alt, ramp, prbs||Select transport layer and link layer test mode through rx_test and tx_test registers of JESD204B IP core.|
off: Normal operation
Link layer test mode:
Transport layer test mode:
Download [svgx_jesd204b_ad9625_ed_14.0.qar ]
Initial release - 27 Oct 2014
Added notes for SYSREF generation - 31 Oct 2014
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