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JESD204B IP Core Stratix V Interoperability Reference Design with AD9625

JESD204B IP Core Stratix V Interoperability Reference Design with AD9625

Last Major Update

First Release - Oct 27th 2014 - Quartus II v14.0 Installed

Design Overview

This reference design demonstrates the implementation of JESD204B IP Core in Stratix® V GX interoperates with AD9625 converter from Analog Devices Inc. (ADI). This design contains one JESD204B duplex IP core and other components that are identical to the components in AN712. Refer to Figure 2 System Diagram of AN712. In this reference design, where LMF = 811 (generic 8 lane mode on ADC), S=4, K=32 and descrambler is on, the data rate of transceiver lanes is 6.25 Gbps. The oscillator on AD9625 EVM provides 2.5GHz device clock to the ADC; ADC divides this clock by 4 and supplies 625MHz device clock to FPGA.

Below are the customized components for this reference design:

  • A QSYS based control unit that provides reset sequence for the IP core. This reset sequence is dictated by the reset procedure in main.tcl. IP core configuration can be implemented in this reset procedure, before the link reset is de-asserted. In this example, the test mode is set to ramp test pattern. The control unit also gathers IP core interrupt and pattern checker status, enable/disable internal serial loopback for duplex IP core. It has a 4-wire SPI master interface to configure the converter.
  • A 4-wire to 3-wire SPI interface conversion circuit using ALTIOBUF Megafunction. Natively, the AD9625 is a 3-wire SPI slave.
  • The SYSREF generator in FPGA generates SYSREF pulses to both the ADC and JESD204B IP core. The SYSREF pulses frequency is 1*LMFC = (FPGA link clock * 4)/(F*K) = 625/32 = 19.53125 MHz.
  • The sysref_delay module (not shown in block diagram below) delays the SYNC~ de-assertion by JESD204B IP core to allow LMFC counter in ADC to become stable before the transmission of ILAS begins. This is accomplished by blocking a number of SYSREF pulses as specified by the SYSREF_DELAY parameter. This delays the SYSREF pulse detection by the IP core and de-assertion of SYNC~ signal.

Note: If SYSREF is provided by external clock source that supplies the device clock to ADC, the rework instruction is available from AD9625 EVM web link below. Due to this

reason and a more convenient hardware setup, the SYSREF is generated by FPGA. However, the common practice in JESD204B application is to source SYSREF from the clock

source that provides device clock to the subsystem.

System Diagram- SV_AD9625_ref_design_blk_diagram.jpg (Click here for image)

Hardware Requirements

Software Requirements

  • Quartus II 14.0 or later with JESD204B IP Core installed

Running the Design

1. Download the design file in the link below.

2. Set up the hardware by connecting AD9625 EVM into the FMC port of Stratix V Advanced Systems Development Board. Refer to Figure 1 Hardware Setup of AN712.

Note: The latest version of AD9625 EVM (AD-FMCADC2-EBZ FMC) from ADI has a 2.5GHz on-board oscillator. Hence, external clock source is not needed.

The setup in AN712 requires external clock source because the older version of AD9625 EVM doesn't have on-board oscillator.

3. Launch SignalTap and configure the first FPGA in JTAG chain with /output_files/svgx_jesd204b_ad9625_ed_14_0.sof. in svgx_jesd204b_ad9625_ed_14.0.qar

4. In SignalTap, at the rx_link instance, click Run Analysis icon below the menu bar.

5. Launch system console and type source main.tcl in the system console window. Then type these commands in sequence:


output_sysref 1


6. The SignalTap is triggered when rising edge of rx_dev_sync_n is detected. The JESD204B link enters user data phase when dev_lane_aligned signal is asserted.

7. ADC test pattern generator transmits ramp test pattern. The test pattern can be observed at jesd204_rx_dataout bus at rx_trpt instance in SignalTap.

8. After the JESD204B link is up, optionally you can turn off the SYSREF pulses by typing output_sysref 0 command in system console window.

Additional information

You can run this reference design in internal serial loopback mode by typing sloopback 1 in the system console window.

System console commands:

Command NameArgumentDescription
config_spi_slaveNot applicableConfigure converter through SPI programming interfaces.
resetNot applicableGlobal reset. It sequences the reset for JESD204B IP core and other components in the reference design. JESD204B IP core configuration prior to de-assertion of link reset can be executed in this procedure.
output_sysref0-1Output SYSREF pulses.

0: Disable (default)
1: Enable

sloopback0-1Internal serial loopback.

0: Disable (default)
1: Enable

set_scr0-1Set JESD204B IP core descrambler bit in ilas_data1 register

0: Disable
1: Enable

read_statusNot applicableRead the status of pattern checker's error signal, JESD204B IP core's interrupt signals and core PLL's locked signal.
read_rxstatus0-7Read JESD204B IP core rx_status<0..7> register (read back data in hexadecimal number).

For example, read_rxstatus 0 reads the content of rx_status0 register.

read_rx_ilas_data1, 2Read JESD204B IP core ilas_data<1,2> register (read back data in hexadecimal number).

For example, read_rx_ilas_data 1 reads the content of ilas_data1 register.

read_rx_err0, 1Read JESD204 rx_err<0..1> register (read back data in hexadecimal number) and display the error message if any. Error status in the entire RX IP core.
read_rbd_countNot applicableRead RBD value from rx status 0 register (read back value in decimal number).
read_rx_sysref_statusNot applicableRead SYSREF detection status for SYSREF Single Detection mode.
reinit_rxNot applicableReinitialize RX link by setting bit 1 of syncn_sysref_ctrl register. This bit will automatically be cleared once link reinitialization is completed.
set_testmodeoff, k28.5, d21.5, alt, ramp, prbsSelect transport layer and link layer test mode through rx_test and tx_test registers of JESD204B IP core.

off: Normal operation

Link layer test mode:
k28.5: A continuous sequence of /K28.5/ characters
d21.5: A continuous sequence of /D21.5/ characters

Transport layer test mode:
alt: Alternate checkerboard test pattern at pattern generator/checker.
ramp: Ramp test pattern at pattern generator/checker.
prbs: PRBS test pattern at pattern generator/checker. The POLYNOMIAL_LENGTH and FEEDBACK_TAP parameters are set at the parameter declaration section of

Link to the Design Files

Download [svgx_jesd204b_ad9625_ed_14.0.qar ]


Initial release - 27 Oct 2014

Added notes for SYSREF generation - 31 Oct 2014

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Last update:
‎06-21-2019 07:50 PM
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