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JESD204B IP Core Stratix V Interoperability Reference Design with DAC37J84

JESD204B IP Core Stratix V Interoperability Reference Design with DAC37J84


Last Major Update

Second Release - December 15th 2014 - Quartus II v14.1 Installed

First Release - September 17th 2014 - Quartus II v14.0 Installed


Design Overview

This reference design demonstrates the implementation of JESD204B IP Core in Stratix® V GX interoperates with DAC37J84 converter from Texas Instruments Inc. (TI). This design contains one JESD204B duplex IP core and other components that are identical to the components in AN719. Refer to Figure 2 System Diagram of AN719. In this reference design, where LMF = 841, S=1, K=32 and scrambler is on, the data rate of transceiver lanes is 12.288 Gbps. The LMK04828 clock generator provides 307.2 MHz device clock to the FPGA and 1228.8 MHz device clock to the DAC37J84 device. The LMK04828 provides SYSREF pulses to both the DAC and FPGA. A wire connects between J21 pin 1 on DAC37J84 EVM (SYNC_N_AB pin) and HSMC breakout board header pin 3 to transmit the sync_n signal from DAC37J84 to FPGA 2. The FPGA 2 acts as a passthrough to deliver sync_n signal to FPGA 1. FPGA 1 interfaces the DAC. The DAC37J84 operates in LINK0 only mode (single link) in all configurations.

A graphical user interface (GUI) that runs on system console, called the JESD204B IP Toolkit is included in this reference design that is compiled with Quartus II v14.1 and beyond. The command line system console scripts, main.tcl and the supporting TCL scripts are located in cmd_line_scripts folder is an alternative to run this reference design if you do not want to use the JESD204B IP Toolkit.



System Diagram SV_DAC37J84_ref_design_blk_diagram.jpg


Hardware Requirements


Software Requirements

  • Quartus II 14.1 or later with JESD204B IP Core installed
  • DAC3XJ8X EVM GUI. Refer to Software section of the EVM web site above.


Running the Design

1. Download the design files in the links below.

2. Set up the hardware by connecting DAC37J84 EVM into FMC port of Stratix V Advanced Systems Development Board. Refer to Figure 1 Hardware Setup of AN719.

3. Configure the second FPGA in JTAG chain with the sync_n_transfer.sof file from the sv_as_passthru.zip.

Note: The FPGA 2 must be configured prior to connecting the wire that carries the sync_n signal to the HSMC breakout board header.

Verify that the voltage at the targeted header pin is less than 1.8 V. Refer to the DAC37J84 datasheet for the absolute maximum

rating of SYNC_N_AB pin.

4. Connect a short wire between J21 pin 1 on DAC37J84 EVM (SYNC_N_AB pin) and HSMC breakout board header pin 3 to transmit the sync_n signal from DAC37J84 to FPGA 2.

5. Launch SignalTap and configure the first FPGA in JTAG chain with /output_files/svgx_jesd204b_dac37j84_ed_14_1.sof in svgx_jesd204b_dac37j84_ed_14.1.zip.

6. Launch the DAC3XJ8X EVM GUI.

7. At the Quick Start tab, click 1. Program LMK04828 and DAC3XJ8X button. Refer to Figure 3 of AN719.

8. Download the File:841 iot.zip EVM configuration file for additional customized settings for the DAC37J84 and LMK04828.

9. Go to Low Level View tab and click the Load Config button. Refer to Figure 10 of AN719.

10. Select the configuration file you just downloaded and click OK.

11. If you are using the JESD204B IP toolkit, execute the following steps. If you are using command line system console script, skip step 11 and go to step 12.

a. Launch system console and type source main_gui.tcl in the system console window. The GUI takes ~1 minute to be fully loaded into system console window.

b. After the GUI is fully loaded, select User Test Pattern from the drop down list of Pattern Generator Mode in Main Control tab.

c. In TX IP Configurations tab, enter F1F1 in the User Test Pattern 0 text field at TX Test Control section.

d. Go back to Main Control tab, click Global Reset button at the top row of this tab.

12. If you are using command line system console script, execute the following step. If you are using IP Toolkit GUI, skip step 12 and go to step 13.

a. Launch system console and type cd cmd_line_scripts in the system console window.

b. Type source main.tcl, then type reset.

13. At SignalTap, at the tx_link instance, click Run Analysis icon below the menu bar.

14. At the EVM GUI Quick Start tab, click 2. Reset DAC JESD core then click 3. Trigger LMK04828 SYSREF

15. The SignalTap is triggered when rising edge of sync_n is detected. The JESD204B link is up and pattern generator is transmitting short transport layer test pattern!!

16. At the EVM GUI, go to Alarms and Errors sub tab under DAC3XJ8X Controls tab. Click Clear Alarms and Read button. None of the error LED should be lighted. Refer to Figure 9 of AN719.

Note: You can view a demonstration video clip for using the JESD204B IP Toolkit on this reference design at YouTube: http://youtu.be/NfIz0iv1Bug

Exit the system console if you want to re-configure the FPGA.


Additional information

To check the DAC JESD core has received the short transport layer test pattern correctly, additional steps are required to enable the short transport layer checker in DAC through the EVM GUI.

1. Go to Low Level View tab. Select config2 from the DAC3XJ8X device in Register Map list box.

2. At bit 12 of the Register Data section, check the mem_shorttest_ena checkbox and click the Write Register button. Refer to Figure 10 of AN719.

3. Go to Alarms and Errors sub tab under DAC3XJ8X Controls tab. Uncheck the Short Test Error checkbox for each lane in Alarm Masking section. Refer to Figure 9 of AN719.

4. The Short Test Error LED should not be lighted.


Command line system console commands in main.tcl:

Command NameArgumentDescription
resetNot applicableGlobal reset. It sequences the reset for JESD204B IP core and other components in the reference design. JESD204B IP core configuration prior to de-assertion of link reset can be executed in this procedure.
sloopback0-1Internal serial loopback.

0: Disable (default)
1: Enable

set_scr0-1Set JESD204B IP core descrambler bit in ilas_data1 register

0: Disable
1: Enable

read_statusNot applicableRead the status of pattern checker and interrupt signals from JESD204B IP core.
read_txstatus0-2Read JESD204B IP core tx_status<0..2> register (read back data in hexadecimal value).

For example, read_txstatus 0 reads the content of tx_status0 register.

read_tx_ilas_data0-2, 4, 5, 8, 9, 12Read JESD204B IP core ilas_data<0..2,4,5,8,9,12> register (read back data in hexadecimal value).

For example, read_tx_ilas_data 1 reads the content of ilas_data1 register.

read_tx_errNot applicableRead JESD204 tx_err register (read back data in hexadecimal value) and display the error message if any. Error status in the entire TX IP core.
set_testmodeoff, k28.5, d21.5, alt, ramp, prbs, cons, sineSelect transport layer and link layer test mode through rx_test and tx_test registers of JESD204B IP core.

off: Normal operation

Link layer test mode:
k28.5: A continuous sequence of /K28.5/ characters
d21.5: A continuous sequence of /D21.5/ characters

Transport layer test mode:
alt: Alternate checkerboard test pattern at pattern generator/checker. The test pattern checker in DAC doesn't support this test mode.
ramp: Ramp test pattern at pattern generator/checker. The test pattern checker in DAC doesn't support this test mode.
prbs: PRBS test pattern at pattern generator/checker. The POLYNOMIAL_LENGTH and FEEDBACK_TAP parameters are set at the parameter declaration section of jesd204b_ed.sv.The test pattern checker in DAC doesn't support this test mode.
cons: Short transport layer test pattern at pattern generator. For F=1, constant pattern 0xF1 is generated by FPGA and checked by DAC JESD core short transport layer test pattern checker.
sine: Sine wave test pattern at pattern generator. Monotone sine wave is visible at the output of the DAC analog channels.


Link to the Design Files

Download [svgx_jesd204b_dac37j84_ed_14.1.zip ]

Download [sync_n_transfer.zip]

Archive [svgx_jesd204b_dac37j84_ed_14.0.zip ]


History

Fixed the links to the design files. (2014-09-26 kkaibara)

Includes JESD204B IP Toolkit in v14.1 reference design. Add SDC constraint and pipeline registers for SYSREF. Update jesd204b_ed.sv. (2014-12-15 welho)


© [2014] Altera Corporation. The material in this wiki site or document is provided AS-IS and is not supported by Altera Corporation. Use the material in this document at your own risk; it might be, for example, objectionable, misleading or inaccurate.

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