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JESD204B Megacore Reference Design for Arria V devices

JESD204B Megacore Reference Design for Arria V devices


Last Major Update

First Release - July 24th 2014 - Quartus II v14.0 Installed


Design Overview

This reference design demonstrates the implementation of JESD204B MegaCore in Arria® V GT interoperates with ADC AD9250 converter from Analog Devices Inc. (ADI). This design contains one JESD204B duplex instance and other components that are identical to the components in AN696. Instead of using the control unit to configure the ADC, this design demonstrates run-time configuration of the ADC using system console.


System Requirements


Running the Design

1. Set up the hardware by connecting ADC AD9250 converter card into FMC port of Arria V GT development board.

2. Download the design file in the link below.

3. Configure the second FPGA in JTAG chain with /output_files/avgt_jesd204b_ad9250_ed_14_0.sof.

4. Launch system console and type source main.tcl in the system console window.


5. Using System Console, configure the ADC AD9250 device to LMF=222 configuration by type in "config_adc_222" command. After that, type in the "reset" command to reset the whole FPGA design system.


Additional information

Several modifications are made to jesd204b_ed.sv, control_unit.sv and Qsys design to move SPI programming function from control unit to system console. The changes are: 1. Comment out the SPI master component at jesd204b_ed.sv.

2. Comment out these SPI/ROM related states from the finite state machine within the control unit design files generated from the example design. For further details, please refer to the control_unit.sv attached in the design here.

3. Migrate all programming sequences for the ADC AD9250 from the ad9250_222.mif(located inside \control_unit\ directory of reference design AN696) to the TCL script(main.tcl) to enable for run-time reconfiguration through system console command. Line 47-92 from the procedure config_adc_222 in the main.tcl indicates the whole programming sequences for the ADC AD9250 converter card.

4. Add SPI master to Qsys at jesd204b_avmm_interface.qsys.


Link to the Design Files

Download [avgt_jesd204b_ad9250_ed.zip]

© [2013] Altera Corporation. The material in this wiki page or document is provided AS-IS and is not supported by Altera Corporation. Use the material in this document at your own risk; it might be, for example, objectionable, misleading or inaccurate.

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‎06-21-2019 08:02 PM
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