This example design is a slight modification of the default FPGA design provided with the BeMicro SDK. It has been updated to include a NIOSII/F with MMU, a TLB memory (required for use with the MMU), and the SDCard interface was changed to use the slower SPI interface for expediencies sake.
Please note that this is purely provided as an example. I strongly urge that you read all of linux related documentation on the AlteraWiki for information regarding building both a SOPC Builder system that meets the requirements for running Linux on the NIOSII, as well as building the linux image.
In the diagram above you will also notice that the BeMicro SDK uses a Mobile DDR controller. This controller is provided by Microtonix, and evaluation for the IP core can be requested from the following link (www.microtronix.com/ip-cores/arrow-bemicro-memory-controller-evaluation-license). A license is required to recompile the design, however I have provided a precompiled SOF with the project.
A precompiled image is provided with the files in the download section. To run the design, please follow these steps.
Program the FPGA via quartus or the command line
In an NIOSII Shell, change directory to the path with the precompiled image (zImage.initramfs.gz)
Run the nios2-download command, and open a nios2-terminal : (nios2-download -g zImage.initramfs.gz; nios2-terminal)
The Linux prompt will appear after the boot messages. To bring up the ethernet interface, type "ifconfig eth0 192.168.1.12 up". The default system does start telnet. Please choose an ip address appropriate to your network.
Currently the following hardware is supported in the precompiled image: