Design Example: Chip ID Reading using AVST Mailbox IP in Intel Agilex® FPGA

This design example shows the Chip IP reading functionality using AVST Mailbox IP in Intel Agilex® FPGA Development Kit. Chip ID reading functionality is implemented in Verilog, and connection with AVST Mailbox IP is required to communicate with Flash Memory.

The design example may be found in the Intel® FPGA Design Store at https://www.intel.com/content/www/us/en/design-example/763981/intel-agilex-7-fpga-chip-id-reading-using-avst-mailbox-ip.html.

The attached document "Chip ID Reading using AVST Mailbox IP in Agilex.pdf" provides more details on using the design example.

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