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Mapping SRLs to registers, MLABs, or Block RAMs Arria 10 Example

Mapping SRLs to registers, MLABs, or Block RAMs Arria 10 Example

This page is dedicated towards providing an example Arria 10 design that maps SRL elements into registers, MLABs, or Block RAMs.

https://community.intel.com/t5/FPGA-Wiki/Mapping-SRLs-to-registers-MLABs-or-Block-RAMs/ta-p/735754

Arria 10 design example mapping SRL elements is found below. The qar file was created using Quartus version 14.0a10.

File:A10 SRL.qar

Version history
Revision #:
3 of 3
Last update:
‎07-10-2020 07:23 AM
Updated by: