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Memory Technology Device

Memory Technology Device


Use DeviceTree and linux-2.6/Documentation/devicetree/bindings/mtd/mtd-physmap.txt

This page describe the "test-nios2" branch, older branches may not apply.

MTD (see doc at is the driver for various flash devices, such as CFI flash, SPI flash, and NAND flash. You need to enable the specific driver to access the flash. The single or multiple flash chips can be divided in to partitions which can be accessed as char devices /dev/mtd0..3 or block devices /dev/mtdblock0..3.

The CFI flash component should be named as "ext_flash", and the EPCS controller component should be named as "epcs_controller", otherwise you have to modify linux-2.6/arch/nios2/kernel/config.c .

The mtd partition map is located inlinux-2.6/arch/nios2/kernel/config.c. You will need to edit the maps and buswidth for your boards.

The EPCS controller is exactly an Altera SPI interface plus some onchip memory. And the EPCS flash is exactly SPI flash, so we use the SPI driver to access the SPI flash.

Eg, the NEEK has 16 bits data bus, and has partitions defined by the apps chooser, please refer to the user guide.

static struct mtd_partition nios2_partitions[] = {

#elif defined(CONFIG_ALTERA_NEEK_C3)


.name = "romfs/jffs2",

.size = 0x300000,

.offset = 0xd00000,



.name = "catalog",

.size = 0x020000,

.offset = 0,



.name = "application",

.size = 0xb80000,

.offset = 0x180000,



.name = "selector",

.size = 0x160000,

.offset = 0x020000,

.mask_flags = MTD_WRITEABLE, /* force read-only */



static struct physmap_flash_data nios2_flash_data = {

#if defined(CONFIG_ALTERA_NEEK_C3)

.width = 2, /* 16 bits data bus */


If you use epcs controller and your fpga isnot Cyclone or Cyclone II, you must change the epcs reg offset from 0x200 to 0x400 in the config.cabove.

#if (defined(CONFIG_SPI_ALTERA) || defined(CONFIG_SPI_ALTERA_MODULE)) && defined(na_epcs_controller)

#define EPCS_SPI_OFFSET0x200 /* FIXME */ <==change this to 0x400 if your fpga isnot Cyclone or Cyclone II

static struct flash_platform_data nios2_spi_flash_data = {

.name = "m25p80",

.parts = nios2_spi_flash_partitions,

.nr_parts = ARRAY_SIZE(nios2_spi_flash_partitions),


.type = "m25p64", /* depend on the actual size of spi flash */


.type = "m25p16", /* depend on the actual size of spi flash */ <==change this to your spi flash size



In uClinux-dist, run "make menuconfig", change the kernel setting,

Processor type and features -->

Platform (Altera Nios II Embedded Evaluation Kit support) <== change this to your dev board

(Using Modules [M] might not work for some or all of the MTD driver parts)

Device Drivers -->

#### To enable MTD

[*] Memory Technology Device (MTD) support --->

--- Memory Technology Device (MTD) support

[ ] Debugging (NEW)

[ ] MTD concatenating support (NEW)

[*] MTD partitioning support

[ ] RedBoot partition table parsing (NEW)

[ ] Command line partition table parsing (NEW)

[ ] TI AR7 partitioning support (NEW)

*** User Modules And Translation Layers ***

[*] Direct char device access to MTD devices

-*- Common interface to block layer for MTD &apos;translation layers

[ ] TI AR7 partitioning support (NEW)

*** User Modules And Translation Layers ***

[*] Direct char device access to MTD devices

-*- Common interface to block layer for MTD &apos;translation layers

[*] Caching block device access to MTD devices

#### To enable CFI flash

RAM/ROM/Flash chip drivers --->

[*] Detect flash chips by Common Flash Interface (CFI) probe

[ ] Detect non-CFI AMD/JEDEC-compatible flash chips (NEW)

[ ] Flash chip driver advanced configuration options (NEW)

[*] Support for Intel/Sharp flash chips # for neek

[*] Support for AMD/Fujitsu flash chips # others

[ ] Support for ST (Advanced Architecture) flash chips (NEW)

[ ] Support for RAM chips in bus mapping (NEW)

[ ] Support for ROM chips in bus mapping (NEW)

[ ] Support for absent chips in bus mapping (NEW)

Mapping drivers for chip access --->

[ ] Support non-linear mappings of flash chips (NEW)

<*> Flash device in physical memory map

[ ] Physmap compat support

[ ] Generic uClinux RAM/ROM filesystem support (NEW)

[ ] Map driver for platform device RAM (mtd-ram) (NEW)

#### To enable EPCS SPI flash

[*] SPI support --->

--- SPI support

  • SPI Master Controller Drivers ***

[*] Altera SPI Controller

-*- Bitbanging SPI master

  • SPI Protocol Masters ***

[ ] SPI EEPROMs from most vendors (NEW)

[ ] User mode SPI device driver support (NEW)

[ ] Infineon TLE62X0 (for power switching) (NEW)

[*] Memory Technology Device (MTD) support --->

Self-contained MTD device drivers --->

[ ] Support for AT45xxx DataFlash (NEW)

[*] Support most SPI Flash chips (AT26DF, M25P, W25X, ...)

[*] Use FAST_READ OPCode allowing SPI CLK <= 50MHz (NEW)

#### To enable flash filesystem support

File systems -->

Miscellaneous filesystems --->

[*] Journalling Flash File System v2 (JFFS2) support

###### end of kernel config

  1.  user application config

Flash Tools --->

--- MTD utils

[*] mtd-utils

[*] eraseall

In the Boot log you should see:

Altera NDK flash (AMD): Found 1 x16 devices at 0x0 in 16-bit bank

Intel/Sharp Extended Query Table at 0x010A

Intel/Sharp Extended Query Table at 0x010A

Intel/Sharp Extended Query Table at 0x010A

Intel/Sharp Extended Query Table at 0x010A

Intel/Sharp Extended Query Table at 0x010A

Using buffer write method

Using auto-unlock on power-up/resume

cfi_cmdset_0001: Erase suspend on write enabled

cmdlinepart partition parsing not available

RedBoot partition parsing not available

Using Altera NDK partition definition

Creating 4 MTD partitions on "Altera NDK flash (AMD)":

0x00200000-0x00800000: "romfs/jffs2"

0x00000000-0x00200000: "loader/kernel"

0x00800000-0x00c00000: "User configuration"

0x00c00000-0x01000000: "safe configuration"


If you are unsure that the flash range for JFFS2 (see boot log) is empty you can do:

eraseall /dev/mtd0

To use the Flash based file system you do

mount -t jffs2 /dev/mtdblock0 /mnt

If you add an epcs controller, you will be able to access it as mtd under Linux/uClinux. That means, you may update the sof like this,

cp your_fpga.img /dev/mtd0

#assume epcs is mtd0

#your_fpga.img is msb<->lsb byte reversed from rbf

NAND Flash interface

Nand flash can be accessed with a simple IO interface. You may add an Avalon tristate bridge and connect to the attached nand_flash_hw.tcl interface component. Example sopc design , v1.sopc, is also attached.

Top level connection,

.ce_n_to_the_nand_flash_0 (NAND_CE),

.re_n_to_the_nand_flash_0 (NAND_RE),

.we_n_to_the_nand_flash_0 (NAND_WE),

.ale_cle_to_the_nand_flash_0 ( { NAND_ALE,NAND_CLE } ),

.io_to_and_from_the_nand_flash_0 (NAND_IO),

(optional gpio for NAND Ready/Busy signal)

(assume gpio componet in ip/gpio from 


.bidir_port_to_and_from_the_gpio_0 ( { ... NAND_RB, ... } ),

Enable kernel config setting,

[*] Memory Technology Device (MTD) support --->

[*] NAND Device Support -->

[*] Support for generic platform NAND driver

Version history
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Last update:
‎06-25-2019 03:18 AM
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