Altera support device migration between various FPGA sizes in all of their FPGA Families, however there are several rules and limitations when designing a board that you need to be aware of to insure you have the ability to freely use the board with all possible family members.
1: Migration is only possible within the same generation of the family. (IE you can not migrate from a Cyclone II to a Cyclone IV device without changing the board)
2: Migration is only possible for a subset of the family members for a particular package. To see what family members are available in a particular package check the Device Packages and Maximum User I/O's on the device overview page for the family.
3: All IO's are not available for use for all Family members. Some may be No-Connect pins while others may be VCCIO's, VCCINT, or GND's for various family members.
4: All differential pairs/special IO's may not be available on the same pins in all migration family members.
To maximize migration compatibility prior to your board layout here are some simple rules to follow:
Option 1: Build a top level design with all IO's expected in the design. In Quartus, select the target device as well as all possible "Migration" devices. Assign your pinout, and compile the design. Make sure it doesn't give you any migration errors or warnings. Then use the resulting .pin file to build your schematic symbol.
If the pins with differences contains at least one of the following:
VCCINT: treat it as VCCINT.
VCCIOx: treat it as VCCIOx.
GND: treat it as GND
NC: treat is as NC unless another family member has it as one of the above.
If the pin is an IO for all family members but it is associated with a different bank in some cases, it is best to not use that pin unless you can insure the associated banks use the same VCCIO and VREF's.
It is best to reserve any pin that is a VREF in any family member as VREF, even if you are not using the VREF functionality since the timing on these IO's may be different.
Make sure you reserve all the configuration pins used for the configuration mode you plan on using.
If your design requires the use of differiential pairs, validate that a matching p-n set is available on all p-n pairs you plan on using.