Success! Subscription added.
Success! Subscription removed.
Sorry, you must verify to complete this action. Please click the verification link in your email. You may re-send via your profile.
SDI Signal | SDI II Signal | Direction | Description |
---|---|---|---|
rst_tx | tx_rst | Input | No change except for naming for some signals |
phy_mgmt_clk_reset | phy_mgmt_clk_rst | Input | |
phy_mgmt_clk | phy_mgmt_clk | Input | |
tx_serial_refclk | xcvr_refclk | Input | |
txdata | tx_datain | Input | |
enable_crc | tx_enable_crc | Input | |
enable_ln | tx_enable_ln | Input | |
tx_std | tx_std | Input | |
tx_trs | tx_trs | Input | |
sdi_tx | sdi_tx | Output | |
tx_ln | tx_ln, tx_ln_b | Input | |
gxb_tx_clkout | tx_clkout | Output | |
sdi_reconfig_togxb | reconfig_to_xcvr | Input | |
sdi_reconfig_fromgxb | reconfig_from_xcvr | Output | |
tx_status | tx_pll_locked | Output | |
tx_pclk | tx_pclk | Input | SDI: 27MHz(SD), 74.25MHz(HD), 148.5MHz(3G) SDI II: 148.5MHz (SD, HD, 3G) |
tx_datain_valid | Input | New. Driven by tx_dataout_valid | |
tx_dataout_valid | Output | New | |
tx_vpid_overwrite | Input | New feature - Insert Video Payload ID (SMPTE 352M) | |
tx_vpid_byte1 | Input | ||
tx_vpid_byte2 | Input | ||
tx_vpid_byte3 | Input | ||
tx_vpid_byte4 | Input | ||
tx_vpid_byte1_b | Input | ||
tx_vpid_byte2_b | Input | ||
tx_vpid_byte3_b | Input | ||
tx_vpid_byte4_b | Input | ||
tx_line_f0 | Input | ||
tx_line_f1 | Input |
Sdi_tx.png (Click here for image)
The differences in between SDI and SDI II Tx implementation
SDI Signal | SDI II SIgnal | Direction | Description |
---|---|---|---|
rst_rx | rx_rst | Input | No change except for naming of some signals |
phy_mgmt_clk_reset | phy_mgmt_clk_rst | Input | |
phy_mgmt_clk | phy_mgmt_clk | Input | |
rx_serial_refclk | xcvr_refclk | Input | |
sdi_rx | sdi_rx | Input | |
rx_clk | rx_clkout | Output | |
rx_data_valid_out | rx_dataout_valid | Output | |
rx_data | rx_dataout | Output | |
rx_F | rx_f | Output | |
rx_V | rx_v | Output | |
rx_H | rx_h | Output | |
rx_AP | rx_ap | Output | |
rx_eav | rx_eav | Output | |
rx_trs | rx_trs | Output | |
rx_std | rx_std | Output | |
crc_error_y | rx_crc_error_y, rx_crc_error_y_b | Output | |
crc_error_c | rx_crc_error_c, rx_crc_error_c_b | Output | |
rx_ln | rx_ln, rx_ln_b | Output | |
sdi_start_reconfig | rx_sdi_start_reconfig | Output | |
sdi_reconfig_done | rx_sdi_reconfig_done | Input | |
sdi_reconfig_togxb | reconfig_to_xcvr | Input | |
sdi_reconfig_fromgxb | reconfig_from_xcvr | Output | |
rx_video_format | rx_format | Output | Refer to User Guide explanation |
refclk_rate | rx_coreclk_is_ntsc_paln | Input | refclk_rate: "0" for a 148.35MHz rx_coreclk "1" for a 148.5MHz rx_coreclk rx_coreclk_is_ntsc_paln: "0" for a 148.5MHz rx_coreclk |
rx_status | rx_pll_locked, rx_align_locked, rx_trs_locked, rx_frame_locked | Output | Extracted from rx_status[0], [2], [3], [4] |
rx_rst_proto_out | Output | Reset the user receiver downstream logic and receiver protocol block | |
rx_clkout_is_ntsc_paln | Output | Indicate incoming SDI signal "0" = PAL rate, 1/1.000 data rate factor "1" = NTSC rate, 1/1.001 data rate factor | |
rx_coreclk | Input | Connected to reference clock frequency. | |
rx_vpid_byte1 | Output | New feature - Extract Video Payload ID (SMPTE 352M) | |
rx_vpid_byte2 | Output | ||
rx_vpid_byte3 | Output | ||
rx_vpid_byte4 | Output | ||
rx_vpid_byte1_b | Output | ||
rx_vpid_byte2_b | Output | ||
rx_vpid_byte3_b | Output | ||
rx_vpid_byte4_b | Output | ||
rx_vpid_valid | Output | ||
rx_vpid_checksum_error, rx_vpid_checksum_error_b | Output | ||
rx_line_f0 | Output | ||
rx_line_f1 | Output | ||
rx_clkin_smpte372 | Input | New feature - Convert level B to level A (SMPTE 372M) | |
rx_dataout_b | Output | ||
rx_dataout_valid_b | Output | ||
enable_sd_search | Input | Not available in Quartus version 12.1 | |
enable_hd_search | Input | ||
enable_3g_search | Input | ||
rx_anc_data | Output | ||
rx_anc_valid | Output | ||
rx_anc_error | Output | ||
en_sync_switch | Input | ||
rx_xyz | Output | ||
xyz_valid | Output | ||
rx_std_flag_hd_sdn | Output |
Sdi_rx.png (Click here for image)
The differences in between SDI and SDI II Rx implementation
© [2012] Altera Corporation. The material in this wiki page or document is provided AS-IS and is not supported by Altera Corporation. Use the material in this document at your own risk; it might be, for example, objectionable, misleading or inaccurate.
Community support is provided Monday to Friday. Other contact methods are available here.
Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.
For more complete information about compiler optimizations, see our Optimization Notice.