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Military Sensor Example Design

Military Sensor Example Design



This FPGA design is a military application consisting of a transmitter/receiver that sends and receives information via radio frequencies. It includes DSP functions such as digital upconversion and digital downconversion, and has several proprietary high-speed serial protocol interfaces that operate at 6 Gbps, as well as a PCI Express (PCIe) Gen2x4 interface operating at 5 Gbps. The main clock is 150 MHz. The end equipment must operate in harsh environmental conditions, so it requires an Industrial temperature-grade device (rated for operation between -40C and 100C). Accordingly, the power estimation was performed using 100C junction temperature. The table below summarizes the FPGA resource utilization.


Resource Utilization Used in the Arria V PowerPlay Early Power Estimator
Resource Type
Approximate Count
Logic
100K LUTs
Flip Flops
100K
Memory
6 Mbits
DSP Blocks
325 (18x18 multipliers)
IO
277 IO
Transceivers
7 channels at 6 Gbps
4 channel at 5 Gbps (PCIe Gen2x4)










You can review the Early Power Estimator results yourself by downloading this file: File:ArriaV EPE Examples.zip


Enter to win an Arria V FPGA Development Kit by submitting your Arria V PowerPlay Early Power Estimator!


Version history
Last update:
‎06-25-2019 05:23 PM
Updated by:
Contributors