Modular SGDMA

Modular SGDMA

Overview

The modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) consists of three individual cores. Each core is responsible for a particular aspect of a data transfer. Since the core consists of multiple cores, you can replace any core without redesigning the entire SGDMA. This design example moves multiple memory buffers from one location in DDR SDRAM to another. The throughput of the memory copy is measured and displayed to the console. Since the modular SGDMA buffers descriptors, the overhead of transferring multiple buffers is minimized.

To use the supplied design example, you will need a Nios® II Embedded Evaluation Kit, Cyclone® III Edition and the Quartus® II design software version 12.1 or later .

Note: As of ACDS 14.0 the modular SGDMA is now offered as a standard Qsys component. It shows up in two flavors: 1) Single monolithic IP and 2) Individual IP. I recommend whenever possible using the monolithic IP core since it's easier to use. I'll maintain this wiki page moving forward for a little while longer since the individual IP are not officially documented so this is the only place to find those documents. Also there is no driver for the monolithic or individual IP at this time so this is the only place you can get a Nios II driver to access it. If you use the ACDS version of the IP you can copy the drivers out of the dispatcher IP directory in the zip file on this page and target the single monolithic IP or the dispatcher in the individual IP.

Updates

Periodically I make updates and fix bugs in the mSGDMA. To stay up to date click the 'watch' button at the top of the page and make sure you have email notifications turned on for your watchlist in your profile settings.

01/14/2015 - The following changes have been made:

Fixed soft reset issue in the read and write master that prevented the internal FIFOs from being reset
Fixed write master burst logic to avoid a replication of 0 times
Enhanced programmable burst count logic to detect when host attempts to write too large of a burst count in the enhanced descriptor
Fixed dispatcher to prevent hosts from corrupting/overflowing dispatcher FIFO when it's full
Removed 'end on EOP or length' field from dispatcher documentation since that feature has always been enabled and is not programmable

07/21/2014 - The following changes have been made to the design files:

Fixed read master channel and error outputs. Bug occurred with the indexing of the output data from the internal FIFO.

11/26/2013 - The following changes have been made to the design files:

Fixed a read master FIFO overflow bug. Bug occurred when the FIFO filled up and unaligned accesses were enabled.
Fixed a simulation only bug in the read master burst logic
Removed warning about enabling burst realignment, this feature is no long necessary when connecting to SDRAMs and I recommend you leave it disabled

4/19/2013 - The following changes have been made to the design files:

Updated the Nios II software to use the new IRQ API
Updated dispatcher so that the busy bit accurately reflects the status of the mSGDMA
Removed all older copies of the mSGDMA, the 12.1 version is the only one provided

11/25/2012 - The following changes have been made to the mSGDMA under the 12_1 directory:

Added Nios II enhanced IRQ API support to the dispatcher block
Fixed bug with ST-->MM transfers where EOP was not qualified by the burst logic properly
Converted design to support Qsys
Added 64-bit addressing support to the hardware and software driver, see dispatcher documentation for more details

Checkin Rules

Frequently I'm asked to add new features to the mSGDMA. Most of these requests would tailor the mSGDMA to one application while being wasteful in terms of logic resources for others so I have been refusing most of them. Typically the only changes most would need to make would be limited to the dispatcher core so usually you can just replace that core while leaving the masters alone. So that we don't 'pollute' this mSGDMA I ask that this page only host the original mSGDMA and only has bug fixes added. If you create a derivative of this mSGDMA please create a new wiki page and add a link to it in the "Derivatives" section below. If I catch anyone adding enhancements to the files on this page I will roll them back so don't bother trying.

Derivatives

Design Specification

The provided design created using Quartus II version 12.1 provides the following IP blocks:

Nios II/f core
Level 1 JTAG debug module
DDR SDRAM
JTAG UART
Timestamp timer
System ID
On-chip memory (code)
Modular SGDMA dispatcher
Modular SGDMA read master
Modular SGDMA write master

MSGDMA_MM_TO_MM_CONFIGURATION.png (Click here for image)

Architecture Overview

Due to the modular design, the modular SGDMA IP is capable of memory-to-memory, memory-to-streaming, and streaming-to-memory topologies. In the memory-to-memory configuration provided by this design example, the read and write master streaming data ports are connected together. Since the masters are connected via Avalon® Streaming (ST) ports, you can configure each master for a different data width or add additional blocks in the data stream. To learn more about the various configurations possible with the modular SGDMA, refer to the user guides of each mSGDMA core.

Features

The modular SGDMA contains the following features:

Per descriptor interrupt enables
Packet transfer length limiting
Video frame buffer parking
Unaligned memory accesses
Static and programmable burst transactions
Datapaths up to 1024 bits wide
Independent transmit and receive descriptor buffering
64-bit addressing support (using Qsys 12.1 or later)
4GB buffer transfers
Programmable stride (word skipping)
Programmable descriptor tagging
User-selected feature set trade off functionality for logic and on-chip memory footprint

Documentation

Each core of the modular SGDMA comes with documentation bundled with the component file. You can launch the documentation (.pdf file) from within the component parameterization wizard or manually locate it in the component directory.