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Multiple Memory interfaces using UniPHY QuartusII 12.0 SP2

Multiple Memory interfaces using UniPHY QuartusII 12.0 SP2 (with shared resources)


Design Overview

The design showcases the implementation of multiple memory interfaces with shared resources, using a 72 bit wide DDR3 interface and 18 bit wide QDRII interface. The design targets Stratix V development board. The Stratix V development board has one 72 bit wide DDR3 interface and one 18 bit wide QDRII interface. The target frequency for DDR3 is 800MHZ and target frequency for QDRII is 350 MHZ. The design is meant as demo style lab and used Quartus II 12.0. The purpose of the lab is for the reader to get a basic understanding of what steps are involved in implementing a shared OCT design between various memory interfaces. After the successful completion of this lab, the User will learn to:

 

1. Generate individual UniPHY memory interface IP instances with UniPHY.

2. Generate a multiple memory interfaces design using DDR3 and QDRII example design with shared OCT.

3. Simulate the multiple memory interface example design.

4. Compile the multiple memory interface example design and test it on the Stratix V development kit


For more information on sharing resources between different protocols, click on the link: www/literature/hb/external-memory/emi_phy_considerations.pdf


                                                                                                                                                                                                                    

                                                                                                                            Figure 1- DDR_QDR_bd_rev1.png (Click here for image)

 

Design Specifications

The table below lists the specifications for the design:


AttributeSpecifications
Quartus-versionQuartus II v12.0 SP2
FPGA5SGXMA7K2F40C2ES

Memory device

DDR3 SDRAM- (X16 -MT41J128M16HA-125)
                       (X8 – MT41J128M8JP - 125)
For more information, refer to the data sheet: http://www.micron.com/

QDRII SRAM - (CY7C2263KV18-550BZX)
For more information, refer to the data sheet: http://www.cypress.com/

Memory speedDDR3 SDRAM: 800MHZ
QDRII SRAM:   350MHZ
Memory- topology-X72,DDR3 
-X18,QDRII
Memory Layout

DDR3 SDRAM: The memory is laid out in discrete component fashion. Four components are x16 and one component is x8

QDRII SRAM: One component with x18.
Note: The same steps can be used for more components if the board supports.

IP usedDDR3 SDRAM Controller with UniPHY v12.0
QDR II and QDR II+ SRAM Controller with UniPHY v12.0
Development BoardStratix V GX development kit
Note: The ES version of the development kit has been used for the example design.
For  information on the board , refer to the link: 
http://www.altera.com/products/devkits/altera/kit-sv-gx-host.html

Lab Steps

The lab uses Quartus II 12.0 SP2 and has Modelsim set up via NativeLink for simulation. The lab assumes the reader is a competent user of these tools and many of their features.

Five files have been pre-designed for this lab to save time:

1.DDR3 parameter file targeting SV development kit.(params_ddr.v)

2.QDRII parameter file targeting SV development kit.(params_qdr.v).

3.Pin assignments file for multiple memory interface(pin_assignments.txt).

4.LED status file(LED.txt).

5.Module instantiation file (shared_inst.v).

A copy of the example project(Example_Project.zip) and Simulation folder(Simulation_file.zip) has also been provided for user reference.

Files used for this lab (in design generation) are located in the zip file:Multiple_memory_interfaces_Example_design_files.zip

Simlation files are located in the zip file: Simulation_file.zip

The example project is located in the Zip file: Multiple_memory_interfaces_SV_QII_12.0sp2.zip

Design Generation

1. Generate individual UniPHY memory interface IP instances with UniPHY

In this step, we will generate individual UniPHY memory interface IP instances

DDR3 ------->   Master for OCT sharing

QDRII  ------->  Slave for OCT sharing

A. Generating and parameterizing DDR3 memory interface IP instance

1. Start Quartus II. Go to file> create new project wizard. Create a new project.

2. Go to tools and open Megawizard Plug-In Manager. Select “copy an existing custom megafunction variation”.

3. Browse and select"params_ddr.v" in Example design file folder "Multiple_memory_interfaces_Example_design_files". This file contains settings for all the DDR3 parameters to target Stratix V GX development kit. If targeting any other board, use your own settings or keep it as default.

4. Set “ddr_x72_800MHZ” as the name of the output file.

5. Click on finish.

6. It will open DDR3 SDRAM Controller with UniPHY window.

7. In the PHY settings tabs, change the “Memory clock frequency” to 800MHZ.

8. In the PHY settings tabs, change the “Rate on Avalon-MM interface” to Quarter.

9. In the PHY settings tabs, go to Advanced PHY Settings and select “master” in OCT sharing mode. Keep the numbers of OCT sharing interfaces as 1.

10. In the memory Parameters Tab, change the Memory Device speed grade to 800MHZ.

11. In the Board settings Tab, Enable “FPGA DQ/DQS package skews de-skewed on board”. Also Enable “FPGA Address/Command package skews de-skewed on board”

12. Keep all the other parameters as default.

13. Click on finish and then click on generate.

14. Click on Exit.

15. Close the dialogue box which appears after that.

B. Generating and parameterizing QDRII memory interface IP instance

1. Go to tools and open Megawizard Plug-In Manager.

2. Select “copy an existing custom megafunction variation.

3. Browse and select "params_qdr.v” in Example design folder "Multiple_memory_inetrafces_Example_design_files". This file contains settings for all the QDRII parameters to target Stratix V development kit. If targeting any other board, use your own settings or keep it as default.

4. Set “qdr_x18_350MHZ” as the name of the output file.

5. Click on finish.

6. It will open QDR II and QDR II+ SRAM with UniPHY window.

7. In the PHY settings tabs, go to Advanced PHY Settings and select “slave” in OCT sharing mode.

8. The core voltage for DDR3 and QDRII needs to be same for OCT sharing i.e. 1.5V HSTL. To change the core voltage, go to the PHY settings tabs, then go to Advanced PHY Settings and select “1.5V HSTL” in I/O standard.

9. Keep all the other parameters as default.

10. Click on finish and then click on generate.

11. Click on Exit.

12. Close the dialogue box which appears after that.


2. Generate a multiple memory interfaces design using DDR3 and QDRII example design with shared OCT

To create a multiple memory interfaces design with DDR3 and QDRII, perform the following steps:

A. Synthesize the individual memory example designs

1. Go to file > Open project.

2. Browse to qdr_x18_350MHZ_example_design/example_project and select qdr_x18_350MHZ_example.qpf and click open.

3. Go to processing > start > start analysis & synthesis

4. Browse to ddr_x72_800MHZ_example_design/example_project and select ddr_x72_800MHZ_example.qpf and click open.

5. Go to processing > start > start analysis & synthesis.

B. Create a multiple memory interfaces top level file:

If you open the top level Verilog example file (ddr_x72_800MHZ_example.v) for DDR3, you will see two instances (one master and one slave).Same is true for QDRII (qdr_x18_350MHZ_example.v) as well.

In the parameter window, when we say master or slave for OCT sharing, Quartus II creates both master and slave instances of same protocol.

In this example, we will modify the top level example design file for DDR3 and replace the slave of DDR3 with the slave of QDRII.

The steps for this are as follows:

Remove all the original instances of the slave from “ddr_x72_800MHZ_example.v


1. Go to ddr_x72_800MHZ_example_design/example_project/ ddr_x72_800MHZ_example and open ddr_x72_800MHZ_example.v

2. From the port list, remove the signal pll_ref_clk_1. Also, remove all the signals withprefix as memory_1_, emif_status_1, drv_status_1_.

3. Remove all the wire names with prefix as if1_ and d1_.Remove wire name “rst_controller_001_reset_out_reset”.

4. Remove the module instance ddr_x72_800MHZ_example_if1 with instance name “if1”.

5. Remove the module instance ddr_x72_800MHZ_example_d0 with instance name “d1”.

6. Remove the module instance altera_merlin_master_translator with instance name “d1_avl_translator”.

7. Remove the module instance altera_merlin_slave_translator with instance name “if1_avl_translator”.

8. Remove the module instance altera_reset_controller with instance name“rst_controller_001”.

Remove all the original instances of the master from “qdr_x18_350MHZ_example.v”


1. Go to qdr_x18_350MHZ_example_design/example_project/qdr_x18_350MHZ_example and open qdr_x18_350MHZ_example.v.

2. From the port list, remove pll_ref_clk_1, oct_1_rzqin, global_reset_n, soft_reset_n. Also, remove all the port signals with prefix as memory_1_, drv_status_1_, emif_status_1.

3. Remove all the wire names with prefix as if1_ and d1_. Remove wire name “if1_oct_sharing_seriesterminationcontrol”, if1_oct_sharing_seriesterminationcontrol “rst_controller_001_reset_out_reset”.

4. Remove the module instance qdr_x18_350MHZ_example_if1 with instance name “if1”.

5. Remove the module instance qdr_x18_350MHZ_example_d0 with instance name “d1”.

6. Remove the module instance altera_merlin_master_translator with instance name“d1_avl_w_translator”

7. Remove the module instance altera_merlin_slave_translator with instance name “if1_avl_w_translator”.

8. Remove the module instance altera_merlin_master_translator with instance name “d1_avl_r_translator”.

9. Remove the module instance altera_merlin_slave_translator with instance name “if1_avl_r_translator”.

10. Remove the module instance altera_reset_controller with instance name “rst_controller_001”.

11. Change the name of port list by adding 1 in the end so that signal name will not be the same when we will copied it to ddr_x72_800MHZ_example.v .For example, input port pll_ref_clk will become pll_ref_clk1.

12. Change the name of all the wires by adding 1 in the end so that wire name will not be the same when we copied it to ddr_x72_800MHZ_example.v.For example, wire if0_afi_clk_clk will become if0_afi_clk_clk1.

13. Also make sure to make changes in wire name in the port list of all the module instantiation like qdr_x18_350MHZ_example_if0, qdr_x18_350MHZ_example_d0, altera_merlin_master_translator, altera_merlin_slave_translator, altera_reset_controller. For e.g. .pll_ref_clk (pll_ref_clk1).

14. Make sure, we do not change names for global_reset_n and soft_reset_n as same resets are used for both DDR3 and QDRII. Keep it as

.global_reset_n (global_reset_n),

.soft_reset_n (soft_reset_n),

15. In the module instance qdr_x18_350MHZ_example_if0, replace if1_oct_sharing_seriesterminationcontrol1 with if0_oct_sharing_seriesterminationcontrol (OCT control signal will now come from DDR3 master).

16. In the module instance qdr_x18_350MHZ_example_if0, replace if1_oct_sharing_parallelterminationcontrol1 with if0_oct_sharing_parallelterminationcontrol (OCT control signal will now come from DDR3 master).

17. Change the module instance name of “qdr_x18_350MHZ example_if0” from if0 to if1.

18. Change the module instance name of “qdr_x18_350MHZ example_d0” from d0 to d1.

19. Change the module instance name of “altera_reset_controller” from rst_controller torst_controller1.


Merge “qdr_x18_350MHZ_example.v” and “ddr_x72_800MHZ_example.v” into “ddr_x72_800MHZ_example.v”

1. Copy all the port list, wires and module instances from qdr_x18_350MHZ_example.v to merge into ddr_x72_800MHZ_example.v

2. Close qdr_x18_350MHZ_example.v (**do not save it).

3. Save ddr_x72_800MHZ_example.v.

C. Include the QDRII project files into DDR3 project and run analysis & synthesis

1. Go to Project>add/remove files from the project.

2. Browse to qdr_x18_350MHZ_example_design/example_project. Select qdr_x18_350MHZ example.qip and click on Add. Click OK.

3. Run analysis and synthesis. After successful completion of synthesis, click OK.


 3. Simulate the multiple memory interfaces example design

To perform the simulation for example design created in Step no. 2, follow the following steps.

A. Generate the simulation files for individual memory example designs

1. Go to File >Open Projects.

2. Browse to ddr_x72_800MHZ_example_design/simulation, select “generate_sim_example_design.qpf” and click open.

3. Go to tools > Tcl scripts. Select generate_sim_verilog_example_design.tcl and click on run.

4. After the script is executed, click Ok.

5. Go to File >Open Projects

6. Browse to qdr_x18_350MHZ_example_design/simulation, select “generate_sim_example_design.qpf” and click open.

7. Go to tools > Tcl scripts. Select “generate_sim_verilog_example_design.tcl” and click on run.

8. After the script is executed, click Ok.

9. Close the Project.

B. Create a directory for simulation

1. In the main project directory, create a folder named as shared_simulation. This is the folder in which we’ll have all the simulation files.

2. Create 2 subfolders named as submodules_master and submodules_slave.

3. Browse to ddr_x72_800MHZ_example_design/simulation/verilog, and copy the “submodules” folder.

4. Browse to shared_simulation/submodules_master and paste it.

5. Browse to qdr_x18_350MHZ_example_design/simulation/verilog, and copy the “submodules” folder.

6. Browse to shared_simulation/submodules_slave and paste it.

C. Create a top level simulation file

In this Step, we are going to create a top level file for simulation.

Top level file for simulation:

If you open the top level simulation file (ddr_x72_800MHZ_example/simulation/verilog/ddr_x72_800MHZ_ example_sim.v), it consists of following instantiation:

1. Reset source

2. Clock source

3. Example design top level file

4. Status checker

5. Altera’s memory simulation model

In the next few steps, we will create a top level file which instantiate multiple memory interfaces example design (which we just created in Step2), Altera’s memory model for DDR3, Altera’s memory model for QDRII, status checker, reset source and clock source.

The following block diagram will make it clearer:


                                                                                                                                  Figure2- Ddr_qdr_sim1.png (Click here for image)


1. Make a new subfolder folder in Shared_simulation and name it as “verilog”

2. Open Quartus II, navigate to file > new > Verilog HDL file. Click OK.

3. Go to file > Save as “shared_sim.v” in directory “shared_simulation/submodules_master.

4. A dialogue box will appear saying “do you want to create separate project with file”. Select No.

5. Navigate to ddr_x72_800MHZ_example/simulation/verilog and open ddr_x72_800MHZ_example_sim.v

6. Copy the contents of the file and paste it in “shared_sim.v”. Save the file.

7. In the next few steps, we will modify the shared_sim.v.

8. Change the top level module name to "shared_sim".

9. Remove all the wires with prefix as "eo_memory_mem_".

10. Remove the module “ddr_x72_800MHZ_example_sim_e0” with instance name”eo”

11. Remove the module “alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en” with instance name m0.

12. Navigate to qdr_x18_350MHZ_example/simulation/verilog and open qdr_x18_350MHZ_example_sim.v

13. Copy all the wire names withprefix as e0_memory_mem and m0_memory_

14. Paste it in shared_sim.v.

15. Also copy the module “alt_mem_if_qdrii_mem_model_top” with instance name as m0.

16. Paste it in shared_sim.v.

 Modify the multiple memory interfaces example design (created in step2) top level file:

1. Browse to ddr_x72_800MHZ_example_design/example_project/ ddr_x72_800MHZ_example and copy ddr_x72_800MHZ_example.v (top level multiple memory interfaces example design file which we created in Step2)

2. Browse to directory shared_simulation/submodules_master and paste the file. Rename the file as "shared_e0".

3. Open shared_e0.We need to make some modifications in the file.

4. Change the top level module name to “shared_e0”

5. Cut the wires named as if0_afi_clk_clk1, if0_afi_reset_reset1 and paste it in the port list as output wire. For instance, wire “if0_afi_clk_clk1” will become the “output wire if0_afi_clk_clk1”.We will need these signals in top level simulation file.

6. Change the module name from “qdr_x18_350MHZ_example_if0” to “qdr_x18_350MHZ _example_sim_e0_if0”

7. Change the module name from “qdr_x18_350MHZ_example_d0” to “qdr_x18_350MHZ _example_sim_e0_d0”

8. Change the module name from“ddr_x72_800MHZ example_if0” to ddr_x72_800MHZ_ example_sim_e0_if0”

9. Change the module name from“ddr_x72_800MHZ_example_d0” to “ddr_x72_800MHZ _example_sim_e0_d0”

10. Save the file.

Instantiate the modified multiple memory interfaces top level file (shared_e0) in shared_sim


1. Instantiate the top level example design module (shared_e0) in shared_sim.v .Make sure you make the proper wire connections. Copy the module connections from file “shared_inst” in Example design file folder "Multiple_memory_interfaces_Example_design_files".

2. Save the file "shared_sim.v"

D. Create a model-sim set up file to automate the multiple memory interfaces design simulation

In the following steps, modelsim tcl file will be created for simulation.


1. Browse to directory shared_simulation/verilog. Create a new folder and name it as mentor.

2. Navigate to ddr_x72_800MHZ_example_design/simulation/verilog/mentor. Copy the files "msim_setup.tcl" and "run.do".

3. Paste the files in shared_simulation/verilog/mentor. Rename the file “msim_setup.tcl” as “msim_setup_shared.tcl”

4. Open the copied msim_setup_shared.tcl file.

 Automate the multiple memory interfaces design simulation using msim_setup_shared.tcl file

.

1. Look for the word” TOP_LEVEL_NAME”. Change the top level file name to "shared_sim". For Example if the TOP_LEVEL_NAME is “ddr_x72_800MHz_example_sim”, change it to “shared_sim”.

2. Define new path variable named as $QSYS_SIMDIR and $QSYS_SIMDIR1. $QSYS_SIMDIR will point to the DDR3 simulation directory which has all the simulation files in it. $QSYS_SIMDIR1 will point to the QDRII simulation directory which has all the simulation files in it.

3. Set QSYS_SIMDIR to point to the directory (submodules_master). It has all the DDR3 simulation files. Use the tcl command

set QSYS_SIMDIR "C: …/…/shared_simulation/submodules_master"

4. Set QSYS_SIMDIR1 to point to the slave simulation directory (submodules_slave). It has all the QDRII simulation files. Use the tcl command

set QSYS_SIMDIR1 "C: …/…/shared_simulation/submodules_slave"

5. Browse to qdr_x18_350MHZ_example_design/simulation/verilog/mentor. Open the file msim_setup.tcl.

6. Look for the comment “Copy ROM/RAM files to simulation directory”. You will find three hex files. Copy all three commands and paste it in “msim_setup_shared.tcl”.

7. In the copied commands, Change the variable name from “QSYS_SIMDIR” to ” QSYS_SIMDIR1”

8. In the file “msim_setup.tcl”, look for the comment “Compile the design files in correct order”. It contains vlog commands for all the QDRII files. Copy all.

9. Go to msim_setup_shared.tcl and look for the comment ““Compile the design files in correct order”.

10. Paste all the copied commands at the end of all the vlog commands.

11. In the copied commands, Change the variable name from “QSYS_SIMDIR” to ” QSYS_SIMDIR1”

12. Go to “msim_setup_shared.tcl”. Again, look for the comment “Compile the design files in correct order”. At the end of all the vlog commands, add the commands with proper path:

vlog "$ QSYS_SIMDIR/shared_e0.v"

vlog "$QSYS_SIMDIR/shared_sim.v"

13. In the design files, look for the command vlog "$QSYS_SIMDIR/ddr_x72_800MHZ_example_sim.v”. Comment it out.

14. In the design files, look for the command vlog "$QSYS_SIMDIR1/qdr_x18_350MHZ_example_sim.v”. Comment it out.

15. Save the “msim_setup_shared.tcl” file

Run the simulation in modelsim


1. Browse to shared_simulation/Verilog/mentor. Open run.do file.

2. Look for "msim_setup.tcl" and replace all the instances with “msim_setup_shared.tcl”

3. Look for file name “ddr_x72_800MHZ_example_sim.v and replace it with “shared_sim.v”

4. Save the run.do file.

5. Open modelsim, go to file>change directory. Navigate to shared_simulation/verilog/Mentor. Click Ok.

6. In the command prompt, type “do run. do”.

7. It will pop up the modelsim waveform window.


(Note: We can also run DDR3-DDR3 simulation and QDRII-QDRII simulation. For more information on the steps, please refer to following link from external memory handbook: http://www/literature/hb/external-memory/emi_debug_verify.pdf )


4. Compile the multiple memory interfaces example design and test it on the Stratix V development kit

In this step, we will compile the multiple memory interfaces design and test the design on Stratix V FPGA using Stratix V development board. Since, we already modified ddr_x72_800MHZ_example.v (RTL changes), now we need to create .QSF File for the multiple memory interfaces design by modifying the ddr_x72_800MHZ_example.qsf file. To create a .qsf file for the multiple memory interfaces design, follow the following steps:

1. Go to File > open project. Navigate to ddr_x72_800MHZ_example_design/example_project and open “ddr_x72_800MHZ_example.qpf”.

2. Go to assignments > device. Select the option “specific device selected in ‘Available devices list’

3. Select the device “5SGXEA7K2F40C2ES”

4. Go to tools > Tcl scripts.

5. Run../../qdr_x18_350MHZ_example_design/example_project/ qdr_x18_350MHZ example/submodules/ qdr_x18_350MHZ example_if0_p0_pin_assignments.tcl

6. Go to tools > Tcl scripts.

7. Also, run ddr_x72_800MHZ_example_if0_p0_pin_assignments.tcl

8. Go to File > open. Navigate to ddr_x72_800MHZ_example_design/example_project and open ddr_x72_800MHZ_example.qsf. You will see all the DDR3 and QDRII instance and global assignments.

 Assign pin locations to multiple memory interfaces design


1. Open file name “pin_assignments.txt” in Example design folder "Multiple_memory_interfaces_design_files" and copy all the pin assignments in ddr_x72_800MHZ_example.qsf .

2. Save the file.

3. Go to file> open.

4. Navigate to ddr_x72_800MHZ_example_design/example_project/ ddr_x72_800MHZ_ example/submodules and open file “addr_cmd_non_ldc_pad”.

5. Look for the module name “ddr_x72_800MHZ_example_if1_p0_simple_ddio_out ” and replace with “ddr_x72_800MHZ_example_if0_p0_simple_ddio_out ”

6. Navigate to ddr_x72_800MHZ_ example_design/example_project/ ddr_x72_800MHZ example/submodules. Look for the file “ddr_x72_800MHZ example_if1_p0.sdc”.Delete the file.

7. Navigate to qdr_x18_350MHZ_example_design/example_project/ qdr_x18_350MHZ example/submodules. Look for the file “qdr_x18_350MHZ example_if1_p0.sdc”.Delete the file.

8. Go to processing. Click on to “start compilation”.

Generate sof file


1. After the successful compilation, open programmer. Go to tools > programmer.

2. Load the generated .sof file (ddr_x72_800MHZ_example.sof) into the Stratix V FPGA. Look for the file “LED.txt” in Example design folder "Multiple_memory_interfaces_design_files" to verify the correct status of the user defined LED’s (which LED should turn ON or OFF.)


Notes/Comments

For more information about Altera’s current IP offering, refer to Altera’s Intellectual Property website.


Update History

Initial Release – Oct,2012 – Stratix V, Quartus II v12.0 SP2, Multiple Memory interface Using Uniphy.


See Also

List of designs using Altera External Memory IP


External Links

 Altera's External Memory Interface Handbook


Key Words

UniPHY,DDR3 SRAM, Design Example, Multiple Memory, Stratix V.

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