The Nios II Embedded Evaluation Kit, Cyclone III Edition (NEEK) has, as one of its many features, a "Debug" connector that can also be used as an 8-bit bi-directional GPIO port. This is a 10-pin shrouded header located on the LCD Daughter Card next to the RJ-45 Ethernet connector. Unfortunately the documentation for this functionality is limited, hard to find, and somewhat incorrect. This page attempts to clarify the the configuration and use of the GPIO functionality by providing a complete Quartus II/Qsys version 11.0 sp1 hardware design as well as a modified "Count Binary" example Nios II software application to demonstrate the implementation of the GPIO port on the NEEK sytem. The hardware design is an extension of the niosii-ethernet-standard-3c25Triple Speed Ethernet Quartus II project included in the Simple Socket Server Design Example which can be found on Altera's Website at:
Like all the other features on the NEEK LCD Daughter Card, the GPIO signals must pass through the high-speed mezzanine (HSMC) connector to get from one board to the other. In addition, the GPIO (Debug) signals also pass through a bi-directional level shifter (U12) and are controlled by an Altera MAXII CPLD which modifies the connections to these signals depending on the Mode configuration. Consequently, a number of steps must be followed to make the GPIO signals available to the Cyclone III. This project defines and uses the GPIO signals as outputs and excercises them with the modified Count Binary Nios II application. The information provided on this page should make it readilay apparent as to how individual GPIO pins could be change to inputs or bi-directional signals.
Connecting the GPIO to the Cyclone III
The following steps were used to create this project and make the GPIO (Debug) header available to the Cyclone III FPGA:
Download and unzip the Simple Socket Server Design Example files from the link shown above to a new project directory.
From the newly created project directory double-clicktheniosii_ethernet_standard_3c25.qpf to luanch the hardware design in Quartus II.
Launch Qsys from within Quartus II and load the peripheral_system.qsys file.
Modify button_pio component in peripheral_system.qsysBasic Settings to change Width from 2 to 4 to enable buttons 1 through 4.
Modify led_pio component in peripheral_system.qsysBasic Settings to change Width from 2 to 4 to enable LED 1 through 4.
Add a new PIO component in peripheral_system.qsys and rename it gpio_pio.
Modify the newly added gpio_pio component in peripheral_system.qsysBasic Settings with the following settings:
Width = 8
, Direction = Output,
Output Register = Enable individual bit setting/clearing.
Modify peripheral_system.qsysSystem Contents to re-assign base addresses to accommodate the additional button and LED bits plus the added GPIO bits.
Re-generate and save the peripheral_system.qsys.
Open the eth_std_main_system.qsys
Set the peripheral_subsystem component address to 0x00000000(Base) and 0x000000ff(End).
Export the gpio_pio_external_connection as gpio_pio
Re-generate and save eth_std_main_system.qsys
Make the following changes to the Quartus II project:
Update the eth_std_main_system symbol in the Quartus II top level Block Diagram File to incorporate the chages made in Qsys.
In the Pin Planner change button_pio Location from PIN_F1 to PIN_F2
In the Pin Planner change button_pio Location from PIN_F2 to PIN_F1
In the Pin Planner add Node Name gpio and assign it to Location PIN_H2
In the Pin Planner add Node Name gpio and assign it to Location PIN_C1
In the Pin Planner add Node Name gpio and assign it to Location PIN_C2
In the Pin Planner add Node Name gpio and assign it to Location PIN_T16
In the Pin Planner add Node Name gpio and assign it to Location PIN_R16
In the Pin Planner add Node Name gpio and assign it to Location PIN_N15
In the Pin Planner add Node Name gpio and assign it to Location PIN_K5
In the Pin Planner add Node Name gpio and assign it to Location PIN_L5
In the Pin Planner Change button_pio Location from PIN_F1 to PIN_F2
Re-compile the Quartus II project and program the NEEK with the new SOF file.
Enabling the Debug Port
One more step before the GPIO will work, and it comes with a bit of a catch. It seems that in order to conserve resources, the 8 data bits used for the GPIO interface are also used for the LCD video decoder. As they connot server both purposes at the same time, you must select the operating mode suited to your application. For the GPIO and/or Debug option, you must select Mode 1.
A common utility application is provided that allows you to change the EEPROM data or the Mode Control Register value stored in the MAX II Device's user flash memory. Perform the following steps to set the board to Mode 1:
Before using this tool, make sure the USB cable is connected to between the development kit board and the host PC.
From the directory: <install dir>/board_design_files/LCD_multimedia_hsmc/ tools/HMB2_Configuration_Utility/, launch HMB2_CONFIG.exe.
There should be a .sof file in this directory (HMB2_CONFIG.sof) that will automatically download into the FPGA and the application will display Connected when communications is established with the downloaded design. (If any error message is shown, please check the power and USB cable, then press Connect button to re- configure FPGA.)