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Nios II 3C120 Design Example

Nios II 3C120 Design Example

Last Updated

September 7, 2011

Description

This is a hardware design example for the Altera 3C120 development board. This board is currently available in many different bundled packages today that go by these names:

  • Cyclone III FPGA Development Kit
  • DSP Development Kit, Cyclone III Edition
  • Embedded Systems Development Kit, Cyclone III Edition

Any one of the above development kits should contain the 3C120 base board that this example design is intended to run on.

This example design was originally intended to create various designs that could be used in the development and evaluation of Wind River Linux for Nios II. It is being published here for more generic example purposes that may not include the use of Wind River Linux, this has generally just involved re-documenting the design, but not substantially changing the overall design or functionality, so many of the component names and other aspects of the design carry this original design intent for running Wind River Linux.

The primary features of this system when built with the "development" option include the following:

  • Nios II/f CPU, with 32KB I cache and 32KB D cache
  • Low Latency DDR2 Interface, 128MB
  • High Latency DDR2 Interface, 128MB
  • External CFI Flash Interface, 64MB
  • System Timer
  • Altera TSE MAC subsystem with associated SGDMAs
  • Additional Timers, PIOs and UARTs
  • Separate Nios II/e controlled display subsystem which manages the 2 line LCD display, 128x64 graphic display and the user seven segment display

Nios2_generic_3c120_125mhz.jpg (Click here for image)

Contents

This example is published in a minimal source form only; you will need to run the build script to create a full project representation of the design. There is also a PDF document provided with some block diagrams and memory maps that are constructed in the example system.


§ 20110828_nommu_nios2_linux_3c120_125mhz_11.0sp1.tgz - this is a non-mmu version of the 11.0sp1 version of this project. The only difference between this version and the original 11.0sp1 port is that the Nios II processor in this system is built without the MMU. This design is not appropriate for linux development, however it is quite useful for non-linux development. To build this hardware example extract the archive, change directory into the build_scripts directory and run the ./create-this-project.sh script.

§ 20110828_nios2_linux_3c120_125mhz_11.0sp1.tgz - this is an updated version of the 10.1sp1 version into the 11.0sp1 tools release. This is essentially the same DEFAULT_MMU QUAL version of the original design. The most significant change to the port forward into 11.0sp1 was to migrate the SOPC Builder system into Qsys, so this new port is Qsys based, no other substantial changes were made. To build this hardware example extract the archive, change directory into the build_scripts directory and run the ./create-this-project.sh script.

§ 20110211_nios2_linux_3c120_125mhz_10.1sp1.tgz‎ - this is an updated version of the original design into the 10.1sp1 tools release. This is not quite the same build model as the original release, but rather a single specific implementation of the DEFAULT_MMU QUAL version of the design. In porting forward to 10.1sp1, only the required updates and changes were applied to the SOPC system and components to incorporate the 10.1sp1 version of all the IP. One change was made to the TSE MAC configuration to enable the multicast hash table, but other than that, no substantial changes were made. Read the included readme.txt file in the archive for guidance on building this release of this design.

§ 20090508a nios2 linux 3c120 125mhz.tar.gz - the minimal source archive, original release

§ 20090525-nios2 generic 3c120 125mhz.pdf - some minimal documentation of the system



Instructions

Downloading the example

Download the archives you are interested in and place them in a directory on your system that does not include spaces in the path name. The entire path name of this directory must not contain spaces, so on Windows systems you should avoid putting these in the "My Documents" folder, or on your "Desktop" since these locations are subdirectories of the "Documents and Settings" path, and that would mean that these locations inherit the spaces in that part of the path name.

In order to extract the archives after downloading them, it is recommended that you run the "tar -xzf <filename>" command from a bash shell. For linux users you should have ready access to a bash shell. For windows users, you may need to install the Altera development tools to gain access to a bash shell. On Windows it is recommended that you install the Altera Quartus II FPGA development tools along with the IP base suite as well as the Nios II EDS development tools. Once these tool chains are properly installed on your workstation, you can launch a bash shell by running:

"Start -> Programs -> Altera -> Nios II EDS X.x -> Nios II X.x Command Shell"

Once you are in the bash shell, you can "cd" into the directory containing the archives that you've downloaded, and running the following command to extract them:

tar -xzf <archive_filename>

Note that if you use some other archiving software to extract these archives, like WinZip, you may loose the execution privileges on some of the shell scripts within the archives that are used to perform various activities associated with building and using the example. If this happens, you can restore execute privileges from within a bash shell with the command "chmod +x <filename>". It is recommended that you avoid this situation by using "tar" to extract the archives from within a bash shell and avoid using any Windows oriented archive utilities with these archives.

Building the example (this is outdated and only applies to the original system release)

After you have extracted the archive you should be able to locate the shell script "create-NO_MMU_DEV" within the top level of the archive directory. In the bash shell, "cd" into this directory and run this script like this:

./create-NO_MMU_DEV

This script should run and fully create the example design without any errors, however, there is no guarantee that this particular build will meet timing. A timing check is run at the end of the build script and a PASS / FAIL indication should be printed to the console regarding timing closure. If your timing closure fails, there are three things that you can manipulate to remedy this, first and most difficult is the development platform, different versions of Linux can produce different results, and Windows will produce different results from Linux, however, most of us don't have multiple development platforms to throw at any given build to change the timing results. Second, is the Quartus II placement seed, this is rather easy to change in Quartus, and then recompiling the design will tell you if this new seed has been more successful or not. Third, you can change the source code, in this example design this is not very difficult, since the design contains a system ID peripheral, regenerating the SOPC Builder system will alter the timestamp constant in this peripheral and produce a source code change. So you could re-generate the SOPC Builder system and then recompile the design in Quartus and see where that takes your timing closure. Another way to achieve this third option is to simply rerun the "create-NO_MMU_DEV" script from scratch as this will essentially accomplish option 3 from above, and it is this very action that makes the timing closure results unpredictable from build to build.

The "create-NO_MMU_DEV" is a simple bash shell script that invokes other shell scripts and TCL scripts to create the example design. Please examine these scripts to get a better understanding of how the system is built. Once you have built the system, you can examine the resultant Quartus project for information about how the system was constructed and any other details about the SOPC system and Quartus project. Requirements

This is a hardware design example for the Altera 3C120 development board. This board is currently available in many different bundled packages today that go by these names:

  • Cyclone III FPGA Development Kit
  • DSP Development Kit, Cyclone III Edition
  • Embedded Systems Development Kit, Cyclone III Edition

Any one of the above development kits should contain the 3C120 base board that this example design is intended to run on.

The current version of this example has been tested under the 9.0 SP1 release of the Altera development tools.

See Also

·       Simple Socket Server Plus example that runs on this hardware design.

·       Superloop Simple Socket Server Plus example that runs on this hardware design.


© 2011 Altera Corporation.

The material in this wiki page or document is provided AS-IS and is not

supported by Altera Corporation. Use the material in this document at your own

risk; it might be, for example, objectionable, misleading or inaccurate.

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