Nios® II Hardware Mailbox with Interrupts

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Nios® II Hardware Mailbox with Interrupts

Nios® II Hardware Mailbox with Interrupts



Last Updated

Dec 15, 2009

Description

The Nios II Mailbox is loosely based on the one currently available in the SOPC Builder as a standard peripheral. Details on the mailbox are here: http://www.altera.com/literature/hb/nios2/n2cpu_nii53001.pdf

This mailbox has the following features:

  • each side of the mailbox has the ability to generate interrupts (don't need to poll)
  • the mailbox registers themselves are implemented in an M9K block
  • this mailbox design has a small footprint (184 LEs + 1 M9K vs 450 LEs for the standard mailbox)
  • fast transaction processing with simultaneous transactions supported
  • configured to use a single clock with PortA considered to be the master interface of the mailbox

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Last update:
‎06-25-2019 10:14 PM
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