This page provide the example designs in verilog and vhdl for niosII_stratixII_2s60.
The example design that in the nios2eds\examples\verilog\niosII_stratixII_2s60 are fast, full_featured, small and standard design.
The example design that in the nios2eds\examples\vhdl\niosII_stratixII_2s60 are fast, full_featured, small and standard design.
Please refer to NiosII StratixII 2s60 RoHS and NiosII stratixII 2s60ES pages for the verilog and vhdl example designs.
For more complete information about compiler optimizations, see our Optimization Notice.