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Nios II Stratix II 2s60ES

Nios II Stratix II 2s60ES




This page provide the example designs in verilog and vhdl for niosII_stratixII_2s60ES.

verilog:

The example design that in the nios2eds\examples\verilog\niosII_stratixII_2s60ES are fast, full_featured, small and standard design.


vhdl:

The example design that in the nios2eds\examples\vhdl\niosII_stratixII_2s60ES are fast, full_featured, small and standard design.


Please refer to NiosII StratixII 2s60 and  pages for the verilog and vhdl example designs.

Version history
Last update:
‎06-25-2019 10:02 PM
Updated by:
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