This document describes how to use the attached designs to implement a JTAG programmer using a Stratix IV development board and Altera JRunner software.
In particular, this implementation uses two Stratix IV GX development boards. One dev board is configured with a simple SOPC design that runs the JRunner software. The second dev board is programmed from the first by connecting (via a standard 10 pin ribbon cable) from the HSMC debug board (of the programmer) to the standard JTAG header (J8) of the dev board to be programmed.
While it was convenient to use two Stratix IV development boards for demonstration purposes, the basic design/software included in this tutorial can be easily extended to any custom design.
A quick search of the web will show two basic methods that can be used to accomplish this:
1) Use JAM/STAPL software and *.jam or *.jbc files
2) Use JRunner and the raw binary format (*.rbf)
This implementation uses the JRunner solution (version 2.4). The main reason for using JRunner is that the rbf format does not use compression, which allows it to be stored/used directly in/from external flash (like is found on the Stratix IV development board). The JAM/STAPL format is compressed and must then be decompressed into memory. The uncompressed programming file for the Stratix IV device requires nearly 12 megabytes of memory which is not practical (unless a DRAM controller is also implemented). However, with the JRunner solution, as long as there is an External Flash device in the design with 12 Mbytes of free space, this solution can work with < 64Kbyte of on-chip-memory (which could be reduced further by optimizing the JRunner program).
This was compiled and tested with Quartus/SOPC Builder 10.1 sp1.