This page provide the example designs in verilog and vhdl for niosII_stratixII_2s60_RoHS.
The example design that in the nios2eds\examples\verilog\niosII_stratixII_2s60_RoHS are fast, full_featured, small, standard and TSE_SGDMA design.
The example design that in the nios2eds\examples\vhdl\niosII_stratixII_2s60_RoHS are fast, full_featured, small, standard and TSE_SGDMA design.
Please refer to NiosII StratixII 2s60and pages for the verilog and vhdl example designs.
For more complete information about compiler optimizations, see our Optimization Notice.