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Off-chip Memory PLL Tuning Example

Off-chip Memory PLL Tuning Example

This example is a slightly modified version of the [1] currently available on Altera's website. It still only functions (out of the box) on a Stratix II 2s60 (non-RoHS) development kit, but the design has been rebuilt in 9.0sp2 and Software Build Tools (command line flow) support has been added.

Hardware Design Specifications

  • Board support: Nios Development Board, Stratix® II edition (non-RoHS)
    • Instructions are provided for porting the design to your board
  • Device support: Stratix II devices only because of PLL reconfiguration features
    • Not supported on Stratix II EP2S15 because of memory requirements
  • Nios II core: Nios II/e, debug-enabled
  • On-chip RAM: 64 Kbytes
  • SDRAM controller: 32 Mbytes
  • DMA controller: 1
  • PLL: 1
  • PLL reconfiguration controller: 1
  • JTAG UART: 1
  • Timer: 1
  • System ID peripheral: 1

N2-sdram-pll-example.gif (Click here for image)

The concept of the design is to shift the phase delay of the clock connecting to the offchip memory (an SDRAM for this design) across a "window" of time, record the phase delays where the memory tests successfully and then choose the middle area of that "success window" as the "ideal" SDRAM clock phase shift.

Full instructions are included in "readme.txt" in the top-level of the design example.


Version history
Last update:
‎06-25-2019 10:44 PM
Updated by: