About the Arria 10 External Memory Interfaces (EMIF) Debug GUI
The EMIF Debug GUI can be used with the Arria 10 External Memory Interfaces IP and its packaged example design. The following assumes you are using either the DDR3, DDR4, or QDRIV EMIF example design which includes the EMIF IP as well as its respective example design. Steps to create the example design based on a specific EMIF configuration can be found in Altera's External Memory Interfaces Handbook.
In order to fully unlock the capabilities of the EMIF Debug GUI, you must do two things: 1. You must ensure that the EMIF Toolkit is enabled for the EMIF IP. (Steps on how to do this can be found in Altera's External Memory Interfaces Handbook. 2. Include the following line in your project's Quartus Settings File (QSF): set_global_assignment -name VERILOG_MACRO "ALTERA_EMIF_ENABLE_ISSP=1"
This QSF assignment will unlock all of the in-system sources and probes the EMIF Debug GUI relies on to function correctly.
Capabilities of the EMIF Debug GUI
The Arria 10 On-Die Termination Tuning Tool helps find the optimal on die termination settings for an External Memory Interface or EMIF. This includes setting the output drive strength, Dynamic ODT, Rtt Nominal, and Rtt Park settings on the memory side. The user can either manually change these termination settings from the original or let the tool iterate through all possible termination combinations to find the "best" setting. For multirank systems interfacing with an EMIF with more than one ODT signal, the tool can also choose to turn on and off ODT signals which will make bringing up this interface easier.
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Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.