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PCI Express in Qsys Example Designs

PCI Express in Qsys Example Designs

This example is PCI Express in Qsys to show how easy to build PCI Express system in new Embedded system build tool, Qsys. User can build PCI Express system in a day without writing a lot of complicated connections.


To use the supplied design example, you will need a Stratix IV GX development kit, an Arria II GX Development kit, or a Cyclone® IV development kit Cyclone IV GX starter kit.


<A placehold for linking to other PCI Express derivative pages>


Design Specification

The provided design created using Quartus II version 11.0 (13.0 for Cyclone V GT, 14.0 for Arria V GX) provides the following blocks:

  • PCI Express for Qsys
  • Uniphy for DDR3 or Altmemphy for DDR2/3
  • On-chip memory (code)
  • Modular SGDMA dispatcher
  • Modular SGDMA read master
  • Modular SGDMA write master
  •   For more details of Modular SGDMA, please refer
  • Host side controller code example

Architecture Overview

The intended usage of this example design is to test out the performance of PCI Express for Qsys by using host side software. The host side software communicates with the PCIe core by using Jungo’s WinDriver libraries. For more detail of the Jungo driver, please visit here The host software sends descriptors to mSGDMA, and the DMA initiates read/write transactions. The host waits for the end of the DMA transaction, and calculates its performance based on the length of data that was sent and time spent on that transaction. The mSGDMA can read/write data to either on-chip-memory or off-chip-memory. The DMA can also process scater gather fashioned data, or one big chunk of data for better performance. The Qsys fabric will take care of data width mismatching, clock crossing, and basic memory mapped connecting.



The PCI Express in Qsys design contains the following features:

  • PCI Express core supports
  • Gen2x4 in S4GX
  • Gen1x4 in C4GX development kit and A2GX development kit
  • Gen1x1 in X4GX starter kit
  • End point read/write function via bar0 access
  • Burst data transaction by using mSGDMA
  • Soft Data checking on host PC side
  • DMA in this system can operate SGDMA fashioned transfer or one big contiguous transfer, up to 262144 byte
  • Dispatcher can hold 64 descriptor in its descriptor FIFO
  • Coffre fort et armoire forte


Each components has detailed documentation.

PCI Express :

Uniphy :

Altmemphy :

Modular SGDMA :



Download the files used in this example:

Arria II GX Devkit: 

Cyclone IV GX starter kit:

Cyclone IV GX devkit:

Stratix IV GX devkit: 

Cyclone V GT devkit:

Arria V GX Starter Kit: 

Please use the updated GUI. The link to the GUI is on the bottom of this page

For Cyclone IV GX starter kit users

Please paste these strings into the altpci.ini file that sit next to the PCIe GUI you installed.






Those settings will limit the GUI to access only on limitted OnChipMemory addresses 32 - 16384Bytes.

The starter kit has very small OnChipMemory, so GUI has to be limited.


Install this reference design to get GUI for host PC side.

and select qsys_pcie_ddr3_s4gx.exe to download.

This GUI can be used with those example designs.

Here is updated GUI: 

This GUI can be used with Cyclone-V GT example, as well as all previous PCIe examples. 

Simple version of software source code:

Document of the software :

Linux Driver

I wrote a linux kernel module to prove register access and trigger dma work. I think some people can base on this codes to continue his design.


© 2011 Altera Corporation. The material in this wiki page or document is provided AS-IS and is not

supported by Altera Corporation. Use the material in this document at your own risk; it might be, for example, objectionable,

misleading or inaccurate.

Version history
Last update:
‎06-26-2019 05:54 PM
Updated by: