PCI Express protocol decoder

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PCI Express protocol decoder

PCI Express protocol decoder

This is a Verilog protocol decoder for PCI express. It decodes ordered sets, DLLPs and TLPs from the PIPE interface. The purpose is to be able to see the exact packet and time of transmission for PCI Express in simulation to aid in debug. For example, it could be used to check when a memory write is performed due to an MSI interrupt being asserted.

The decoder connects to a single PIPE interface. It supports x1, x2, x4 and x8 interfaces. Connections should be made as follows:Setup and connection to the Altera PCI express IP

Decoder input port Connection to Receiver Connection to Transmitter 

reset !pcie_resetn !pcie_resetn 

clk clk250 for gen1, clk500 for gen2 clk250 for gen1, clk500 for gen2 

rxdatax <name>_rxdata0_ext <name>_txdata0_ext 

rxdatakx <name>_rxdatak0_ext <name>_txdatak0_ext 

rxx_en <name>_rxvalid0_ext <name>_txelecidle0_ext

The decoder only supports the unscrampled interface so the scrambling must be tunred off by setting test_in[2] to 1 in your testbench. If you are using the Altera PCIe BFM it is easiest to set this bit in the BFM where the other test_in assignments are made.

Output files and formatting

The decoder creates three output files at pwd: pcie_logfile.log, pcie_logfile.log_dllp, pcie_logfile.log_tlp. The name of the generated files may be changed by modifying the parameter LOGFILE_NAME in the instantiation.

.log contains all decoded symbols: ordered sets, DLLPs, TLPs

.log_dllp contains only DLLPs

.log_tlp contains only TLPs

Each of these files are csv files which contain the decoded packet fields and the time when the packet was decoded. The full data packet is provided also.


The decoder and a sample testbench may be downloaded from this location: File:Pcie decoder.zip

Current status and future enhancements

The decoder has been used on some real testbenches and works well. I have listed some known problems and enhancements that I have found.

Known Problems

Calculation of packet length is incorrect. Any !!!incorrect length TLP!!! may be ignored

Only Gen1 or Gen2 is supported. Note that Gen2 systems link train at Gen1 speed first, so the first part of link training will not be in your log for Gen2

Data an Address are not yet decoded for memory transactions, the full packet must be inspected.

Future Enhancement ideas

Support Automatic switch between 250MHz and 500MHz clock for gen1 to gen2 switch.


Gen 3 support

Tx and Rx correlation:- This may be easier as a post process of the files using a language like perl.

External Links

PIPE interface specification (Intel)


Altera PCIE resource center

Key Words

PCIE, PCI Express

Version history
Last update:
‎06-26-2019 05:54 PM
Updated by: