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PCI Express to External Memory - Stratix IV ALTMEMPHY DDR3 PCIe Gen1x8

Reference Design : PCI Express to External Memory - Stratix IV ALTMEMPHY DDR3 PCIe Gen1x8

Last Major Update

February 2010, Version 1.3 - Design updated to use DDR3 SDRAM High Performance Controller II (with ALTMEMPHY) IP with PCI Express Gen1x8 IP.

Design Overview

This PCI Express to External Memory reference design demonstrates the operation of Altera's PCI Express MegaCore® function with the ALTMEMPHY-based DDR3 SDRAM memory controller. This design provides a sample interface between the PCI Express Gen 1 x8 link and an external 64-bit SDRAM memory.


If you are looking for a PCIe Gen2 x8 to UniPHY DDR3 reference design, refer to Altera's PCI Express to External Memory Reference Design web page.

PCIe-DDR3-ReferenceDesign-block-diagram.gif (Click here for image)

Design Specifications

The table below lists the specifications for the reference design:

Quartus II version9.1 SP2 
PCIe IPPCI Express Compiler v9.0
DDR3 IPDDR3 SDRAM High Performance Controller v9.1 SP2
Development KitStratix IV FPGA Development Kit - DK-DEV-4SGX230N
FPGA deviceEP4SGX230KF40C2
PCIe ConfigurationGen1 x8
DDR3 Interface Frequency533-MHz / 1066-Mbps
DDR3 Interface width64-bit (four x16 components with fly-by topology)
DDR3 memory deviceMT41J64M16LA-15E





The PCIe MegaCore IP cannot be regenerated and must be used as-is. Regenerating the IP would erase all customizations made to the design to replace internal memory with an external memory interface.


Update History

  • February 2010, Version 1.3 - Design updated to use DDR3 SDRAM High Performance Controller II (with ALTMEMPHY) IP with PCI Express Gen1x8 IP.


See Also


External Links

  1. AN 431: PCI Express to External Memory Reference Design
  2. External Memory Interface Handbook: DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
  3. PCI Express Compiler User Guide

Key words

DDR3, External Memory, PCIe, Stratix IV, Gen1x8, ALTMEMPHY

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Version history
Last update:
‎06-26-2019 10:54 PM
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