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PCIe example designs: How to create enhanced transaction log during simulation

PCIe example designs: How to create enhanced transaction log during simulation

PCIe example designs: How to create enhanced transaction log during simulation

The following procedure is used to generate 2 log files namely tx.log and rx.log that will be helpful for those who would like to debug the TLP and any issues associated with it. These log files show the user the type of transactions done by the TLP without actually having to decode it. The current files are known to be compatible with ModelSim and support all Arria V, Cyclone V and Stratix V Gen 1 and Gen 2 PCIe HIP configurations from Altera.Overview

How to

This section provides a step by step guide on how to create and view the log files using ModelSim. The configuration of the files is similar for both Gen 1 and Gen 2 HIP.

Step 1

The first step is to create a PCIe HIP using Altera Quartus II software and Qsys. When you install Quartus II software, you also install the IP library. This installation includes design examples for Stratix V Hard IP for PCI Express in <install directory>/ip/altera/altera_pcie/altera_pcie_hip_ast_ed/example_design/sv directory (Similarly, for Arria V and Cyclone V: directories av and cv). Here is a brief instruction on how to create a PCIe HIP in Qsys using these design examples.

- First, copy the Qsys file onto your working directory.

- Open Quartus II and then open this Qsys file. Eg: pcie_de_gen1_x8_ast128.qsys

- In the generation tab, use the following settings:

Create simulation model: None

Create testbench Qsys system: Standard, BFMs for standard Avalon interfaces

Create testbench simulation model: Verilog

Enable both ‘Create HDL design files for synthesis’ and ‘Create block symbol file(.bsf)’.

- Click generate.

Once the IP is generated, there should be two subfolders (/testbench and /synthesis) under <working_directory>/<pcie_de_gen1_x8_ast128> (The name depends on the type of IP that has been generated).

Step 2

The next step is to modify the file named altpcietb_bfm_vc_intf.v. This changed file contains tasks pkt_display and data_display which help populate the log files.

- In the console, change directory to <working_directory>/<pcie_de_gen1_x8_ast128>/testbench/<pcie_de_gen1_x8_ast128_tb>/simulation/submodules

- Next, grep “altpcietb_bfm_vc_intf” *.v. This command returns the .v file in the /submodules directory which contains “altpcietb_bfm_vc_intf”. In our example, it is the file named altpcietb_bfm_rp_gen2_x8.v

- Replace the altpcietb_bfm_vc_intf.v portion of this file with File:Altpcietb bfm vc intf.v  and save.

Step 3

Now, we are required to run the simulation on ModelSim. Here is how:

- Open ModelSim and then change directory to <working_directory>/<pcie_de_gen1_x8_ast128>/testbench/mentor

- Source the file named msim_setup.tcl using the command source msim_setup.tcl

- Compile all design files and elaborate the top level design using the command ld_debug

- After the compilation is complete, add the Avalon-ST signals to the wave window.

- Run the simulation by typing the command run –all in the transcript window.

Once the simulation is complete, we can find the log files rx.log and tx.log in the /testbench/mentor directory. The figure below shows one packet in the waveform and correspondingly in the log file.

Snapshot.png (Click here for image)

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Last update:
‎06-26-2019 11:53 PM
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