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PROFINET Getting Started FAQ

PROFINET Getting Started FAQ


What versions of Quartus can I use?

The PROFINET reference design was developed and tested with Quartus II software version 12.0 SP2. Any other version of Quartus may or may not work as expected, and no support is available for any other version of Quartus for this development kit.

What software and PROFINET hardware do I need from Siemens or any other source to get started?

For details, refer to PROFINET IRT: Getting Started with The Siemens CPU 315 PLC.

The design is not compiling for me. What do I do?

Please read the Adding New Design Components to the PROFINET IP application note on building the design. There are a few issues that can cause this that are covered in that application note.

Some modules are undefined when I compile. What is wrong?

Some warnings are acceptable. Please read the Adding New Design Components to the PROFINET IP application note on building the design. There are a few issues that can cause this that are covered in that application note.

What licenses do I need to compile and run?

To compile the Softing IP, you must first setup the appropriate license file. A license file is required for the Softing IP and is provided with the delivered IP. This file can be found in the following:

<ProjectRoot>\hardware\ip_core\licence.dat

You can find detailed instructions on setting up the license file in the Adding New Design Components to the PROFINET IP application note. Look for the "License File Setup" section.

In addition, you will need a NIOS II license to build the out- of-box design, which can be acquired from Altera. The NIOS II IP core can be used in a limited, unlicensed mode using Altera's Open Core Plus (OCP), which allows for unlimited usage as long as the device is connected to a licensed Quartus tool (i.e. tethered to a computer) or in a time- limited capability if untethered.

How do I get a permanent license (CPLD)?

Go to the markets/industrial/automation/ethernet/protocols/ind- multiple-protocols.html Design for Multiple In... web page for instructions on how to obtain a permanent license.

How do I know the design is working?

If the design is working properly without a PLC, the LEDs on the INK board will flash immediately after rebooting the INK, and IP settings will scroll across the LCD.

In order to know if the design is working as expected with a PLC, follow PROFINET IRT: Getting Started with The Siemens CPU 315 PLC.

How do I know the CPLD authentication is working?

This following section describes IP authentication for short term development and how to authenticate the IP beyond the two-hour maximum operational time.

Security Chip

The Softing IP uses an Altera MAX II CPLD as a security chip to ensure that only authorized instantiations of the IP are allowed. However, to facilitate development of the IP, a two-hour evaluation period is integrated into the design, allowing the system to run without the security chip until the two-hour window expires. Once this window expires, a power cycle of the INK will trigger a new two-hour evaluation window. Once the two-hour window expires and no CPLD is attached to the IP, the IP no longer communicates with the PLC or passes traffic through the Ethernet ports.

If you need to run the Softing IP on an INK development board to run longer than the two-hour window, contact your local Altera representative and request a prebuilt/preprogrammed daughter card for the INK board. The daughter card is built on a Terasic Micro MAX II development board with the Softing security authentication programmed on it. With this daughter card attached to the INK board, the system runs past the two-hour window.

Details of this daughter board and its debug features can be found in the "CPLD Daughter Card" section that follows.

CPLD Daughter Card

The Softing IP has a built in time limit that will allow it to run for a two-hour evaluation period, but to run longer, a preprogrammed Altera CPLD must be connected to the Softing IP. A daughter card for the INK based off of the Terasic MAX II Micro Kit is available from Altera representatives.


MAX_II_Micro_Kit.jpg (Click here for image)


This kit has the Softing security chip, but also some additional debug features to help you to confirm the authentication challenge and response are correct. The next section describes those features.

The Terasic MAX II Micro Kit comes with pushbuttons and multi-colored LEDs. These are listed in the following table with the corresponding features for the CPLD Security design.

Board LabelBrief NameColorDetails
led1Out of ResetBlueIndicates the daughter card is out of reset. The system will come out of reset on its own, but it can be placed back into reset using a push button.
led2Clock TogglingGreenThis led will pulse approximately twice a second and is an indicator the clock on the board is working.
led3Challenge ValidOrangeIndicates the Softing IP is sending a challenge request to the CPLD.
led4Response ValidRedIndicates the CPLD is sending a response to the Softing IP.
led5Error PendingBlueIf set, this indicates that an error is waiting to be injected into the system. See Insert Error (button2) below for more details.
led6not used----
led7not Used----
button1rst_system_n--If needed, the CPLD can be held in reset if this button is pressed. Generally, the system should not require a reset.
button2Insert Error--When this button is pressed and then released, internal logic then waits until the next authentication challenge is sent. When this occurs, the response is purposely corrupted forcing the Softing IP to attempt a challenge retry. This can be observed as second set of pulsing LED3 (orange) and LED4 (red).
button3not used----
button4not used----

Procedure to Confirm Correct Authentication Exchange

After the two-hour window has expired, the IP issues a new challenge to the CPLD approximately once a minute. However, before the two-hour window expires, the Softing IP only issues a challenge once, right after reset. The purpose of this single challenge is to allow you to evaluate if the authentication exchange passed or failed without waiting for the two-hour window to expire.

The normal challenge and response will cause led3 (orange) to pulse briefly followed by led4 (red) pulsing briefly. The orange led indicates the Softing IP is issuing a challenge request and the red indicates the CPLD is issuing a response. Each pulse lasts less than half a second. If the Softing IP detects a bad response, it will immediately issue another challenge request. If it continues getting bad responses it will repeat this sequence until the retry timeout occurs (four pulses) and then abort trying to authenticate.

So, by observing the number of orange/red pulses, you can determine if the challenge and response was correct (one pulse of orange/red), or if the challenge response was bad (several pulses of orange and red). To demonstrate this in steps:

  1. Begin with the INK / CPLD daughter card powered down.
  2. Power up the CPLD daughter card via the USB cable. The green led should be pulsing.
  3. Power up the INK by pressing the red "power" button while staring at led4 (red).
  4. Count the number of red only pulses and compare that to the following table.
Red Pulses CountedStateDetails
0UnknownThis could indicate the daughter card is not connected correctly or some kind of connection issue.
1AuthorizedThis is the common, correct authorized state.
2Authorized with one errorThis indicates that one challenge was sent and the response was incorrect but a second challenge yielded a good response. This can happen as part of the Insert Error functionality (button2, above) or due to random noise on the connectors. The system is in an authorized state.
3 or greaterUnauthorizedThis indicates the CPLD is not programmed with the Softing security key. Contact your Altera representative to get the correct board. The system will continue to run for the 2 hour window.

Since the first challenge occurs very quickly after the INK powers up and the FPGA configures, it may be possible that noise on the FPGA I/O during this time may make counting either the orange or red pulses difficult. If this is the case, the best solution is to use the Insert Error feature by pressing button2 in between steps 2 and 3 above. This will cause a second blue LED to be set (led5). When the INK is powered up, the first challenge will be given a bad response which will cause a second challenge to be issued. This makes it easier to differentiate a set of orange/red pulses due to challenge/response verses noise causing random looking pulses.

The challenge/response sequence (orange/red) can be also observed after the two-hour window. The exchange should happen periodically, approximately once every minute.

When I first programmed the design, it worked. After some time, it stopped working. What happened?

The PROFINET reference design from Softing has a time limitation that allows the design to run for two hours, then it stops functioning as expected. Please contact Softing for licensing information.

How does one go about changing the application side of the PROFINET design from Softing and Altera?

Refer to the Adding New Design Components to the PROFINET IP.

Makefile Error: *** multiple target patterns

In the Softing document GettingStarted.pdf, section 4.3 "Debugging the application," describes how to import the software projects into the NIOS II Eclipse IDE using the File > Import > Import Custom Makefile for NIOS II Software Build Tools Project command. Some versions of the NIOS II Build tool incorrectly error out on the Board Specific Package (BSP) Makefile, giving the error Makefile:511: *** multiple target patterns. Stop.

This error is a problem with the GUI version of the tool used for debug, but has not been seen in the command shell versions of the NIOS II Eclipse IDE. The problem will result in an error when any make command is run as shown in the following screenshot:


Nios_II_-_Eclipse_Error.jpg (Click here for image)

 

The quick fix for this is a small edit to the Makefile. Around line 65 of the file <ProjectRoot>\altera_ink_switch \software\application\appl_altera_hal\bsp_ink\Makefile should appear the following line:

ABS_BSP_ROOT := $(call adjust-path-mixed,$(shell pwd))

The above line will work when running from the NIOS II Eclipse IDE command shell. However, when running from the NIOS II Eclipse IDE GUI, change that line to:

ABS_BSP_ROOT := $(call adjust-path,$(shell pwd))

With the above edit, removing -mixed, the Makefile will compile with the NIOS II Eclipse IDE GUI. Making this change effectively breaks the Makefile for the NIOS II Eclipse IDE command shell. So, the Makefile needs to be updated whenever switching between the GUI and the command shell of the NIOS II Eclipse IDE.

Altera has scheduled to fix this issue in Quartus 13.0.

NIOS II Eclipse Path Problems

When invoking the NIOS II Software Build Tool directly from the Windows Start menu, there can be an issue with the tool path configuration. This will result in the NIOS II Eclipse IDE GUI not being able to find certain key executables like nios2-elf-gcc in the following example.


Crop_Nios_II_-_path_problem.jpg  (Click here for image)


The quick fix for this is to always invoke the NIOS II Eclipse IDE GUI eclipse-nios2.exe from the NIOS II Eclipse IDE command shell by first opening the command shell (Start > All Programs > Altera > NIOS II EDS > NIOS II Command Shell) and then opening the GUI by entering the command eclipse-nios2.exe &.

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