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Partial Reconfiguration Example Design with Avalon MM

Partial Reconfiguration Example Design with Avalon MM



This is a PR example design developed on Stratix V GX DSP Dev Kit using ACDS 14.0 Internal host with JTAG Master to Avalon MM

Compilation step: 1. Compile PR_AVMM revision 2. Compile PWM_rev revision

Static region:

PC to send the RBF file to the Partial reconfiguration through USB-Blaster

Total of 1 PR regions with each one contains of 2 personas:

Persona 1: blinking led

Persona 2: PWM led

Here is the System Console GUI and design which will help to simplify the information sending to the system.

System Console GUI tcl File:AVMM PR.tcl

Quartus 14.0 PR design File:PR AVMM.qar



Data/CSR Memory Map Format

NameAddress OffsetWidthAccessDescription
PR_DATA0x016WriteEvery data write to this address indicates this bitstream was sent to the IP.
PR_CSR0x116Read/WriteControls and status registers.

PR_CSR Control and Status Registers

Bit OffsetDescription
0pr_start signal. PR_CSR[0] is de-asserted to value "0" by the IP automatically one clock cycle after it is asserted to streamline the flow as user does not need to manually de-assert this register.
1double_pr signal
2-4status[2:0] signal
5-15Reserved

Please refer to the Altera Partial Reconfiguration Megafunction for more information.

Version history
Revision #:
1 of 1
Last update:
‎06-27-2019 12:11 AM
Updated by:
 
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