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This is a PR example design developed on Stratix V GX DSP Dev Kit using ACDS 14.0 Internal host with JTAG Master to Avalon MM
Compilation step: 1. Compile PR_AVMM revision 2. Compile PWM_rev revision
PC to send the RBF file to the Partial reconfiguration through USB-Blaster
Total of 1 PR regions with each one contains of 2 personas:
Persona 1: blinking led
Persona 2: PWM led
Here is the System Console GUI and design which will help to simplify the information sending to the system.
System Console GUI tcl File:AVMM PR.tcl
Quartus 14.0 PR design File:PR AVMM.qar
Data/CSR Memory Map Format
PR_CSR Control and Status Registers
Please refer to the Altera Partial Reconfiguration Megafunction for more information.
For more complete information about compiler optimizations, see our Optimization Notice.