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Polling SGDMA

Polling SGDMA



Intro

This SGDMA is a modified version of the Altera Avalon SGDMA v10.0 component. It has three added features which may be of interest.

•It has a polling mode where when a non owned descriptor is encountered it can automatically poll on that descriptor until the owned bit is set. 

•The Descriptor address is automatically updated to reflect where the descriptor is being read from. 

•BE32 mode ( Big Endian 32 bit). It automatically swaps the byte lanes and byte eneables to help with compatibility with mixed Endian systems.

Details

To support polling a new control register bit was added (bit 18). When this bit is set the SGDMA will periodically poll (re-read) the first descriptors found that doesn't have the "owned" set, waiting for it to become available. This makes it very easy to add new descriptors at any time. The frequency of the polling is determined by the polling_count (bits 30-20 of the control register). This polling_count value is multiplied by 32 to determine the number of clocks between polls.

BE32 mode is enabled in the GUI and adjustable in software. It swaps the byte lanes of the read and write MM masters as well as byte enables.

All other details of the Polled GDMA are identical to the Altera version, so refer to the Altera documentation.


Compatibility

Has been tested with Quartus 9.1 and 10.0, Qsys 10.1


Installation

Install in the IP subdirectory of your project or in the Atlera/xx.x/ip/other directory.

FIle 

https://www.intel.com/content/dam/altera-www/global/en_US/uploads/3/34/Avalon_polling_sgdma10.1.zip    


© 2010 Altera Corporation. The material in this wiki page or document is provided AS-IS and is not

supported by Altera Corporation. Use the material in this document at your own risk; it might be, for example, objectionable,

misleading or inaccurate.

Version history
Revision #:
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Last update:
‎06-27-2019 12:16 AM
Updated by:
 
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