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With SDRAM ECC (error correcting code), the SDRAM controller will fix single bit error automatically.
The Preloader will now be interrupted and informed about any single bit corrections responding by clearing the interrupt bit.
When double bit errors occur, there is not much can be done by controller or the Preloader.
There is might a chance that processor might fetch the error instructions.
For critical software, user would need to enable the watchdog to overcome this.
Do note that the Preloader will enable the watchdog (based on handoff) and leave it enabled upon exiting.
As of now, the Preloader won't initialize all the SDRAM ECC bits after the ECC is enabled.
This is because the time need for initialization will take 3-5 seconds.
This will be visited at later release on how to speed up the initialization (such as utilizing DMA or cacheline dump method).
Without the initialization, user might get false double bit error when reading from uninitialized memory.
This is applicable for scenario such as cache fill in subsequent bootloader (such as U-Boot).
It is ok for subsequent software to turn off the interrupt for SDRAM ECC as the single bit error will still be corrected by controller.
Subsequent software won't be interrupted whenever ECC errors happen.
To enable the ECC, the user just needs to specify interface width of 40 (32bit + 8bit ECC) or 24 (16bits + 8bit ECC) in Qsys.
With the Preloader now enabling ECC bits, it is possible that false double bit errors will be received in any successive code.
U-boot now disables this interrupt to avoid false errors. At some point in the future, ECC bits will be properly initialized.
Do note that the single bit error still will be corrected by the hardware / SDRAM controller.
Instead of using the hard EMAC PHY that located on the board, you can connect the EMAC to a soft PHY controller within the FPGA.
To enable that, the Preloader is changed to initialize the FPGA interface register within the System Manager.
It enables the interface between the EMAC controller with FPGA's soft IPs such as soft PHY.
This Preloader is updated to initialize the SDRAM ODT registers.
This is required for faster operation of SDRAM such as 533MHz.
This Preloader is updated to allow soft IP access to HPS SDRAM through FPGA2SDRAM port.
It enables the port(s) as told by Qsys instead of all them.
Ultimately, downstream software will need to change these settings based upon changing "soft" FPGA IP needs.
This change updates the Preloader Clock Manager macro.
Although its not a functional defect, it might cause higher current consumption during clock configuration.
This change updates U-Boot's EMAC driver.
U-Boot will put the EMAC controller into reset when configuring the PHY interface select register within System Manager.
It is to avoid potential clock glitch that might cause the EMAC and PHY going into unknown state.
* Note: This change is not rolled into the Preloader that is part of 13.0sp1, but is available via git on rocketboards.org.
Below is the layout of SD card which contain all the boot image.
Location of everything except the Preloader is configurable.
FlashLayout-SDMMC.png (Click here for image)
User can use U-Boot to program or update the boot image within QSPI flash.
% fatload mmc 0:1 <temporary memory location in sdram, example 0x2000000> <filename>.
%sf probe (optional in case you haven't initialize Quad SPI controller before)
%sf erase <start of flash address> <erase size, minimum 0x10000>
For Preloader ->
%sf erase 0x0 0x40000
For U-Boot ->
%sf erase 0x60000 0x40000.
%sf write <memory location specified in step 3> <flash address specified in step 4> $filesize
For Preloader -> sf write 0x2000000 0x0 $filesize
For U-Boot -> sf write 0x2000000 0x60000 $filesize.
FlashLayout-QSPI.png (Click here for image)
This is to support the BootROM's FPGA boot flow.
This is enabled when BSEL = boot from FPGA.
To enable the BootROM's to pass off boot to a preloader residing in the FPGA, you need to properly tie off signals in Qsys and Quartus.
FPGA_ocram.png (Click here for image)
Please refer to the following steps:
To enable a simple and quick memory test after the SDRAM successfully calibrated, just enable the hardware diagnostic mode.
At board/altera/socfpga_cyclone5/build.h, #define CONFIG_PRELOADER_HARDWARE_DIAGNOSTIC (1)
Do note that the value of PHYS_SDRAM_1_SIZE should be in power of 2 (SDRAM device size always in a value of power of 2 too).
User can configure the data and clock skew run time without the need to recompile the source.
Here are the steps:
Invoke U-Boot console
% env set micrel-ksz9021-clk-skew 0xa0d0
% env set micrel-ksz9021-data-skew 0x0
The value will take effect after the restart.
For more complete information about compiler optimizations, see our Optimization Notice.