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Programmable IOE Delay Chain Interface

Programmable IOE Delay Chain Interface

The attached .zip file has a full project and simulation testbench for interfacing to the IOE programmable delay chain. There is also a User Guide that goes into detail on the implementation.

The basic concept is that the delay chains require user logic to control their configuration.  This design has a state-machine for doing this configuration, but also has a simple register map for controlling which I/Os are configured and what value they should be configured with.  This allows a system processor, whether on or off chip, to dynamically configure the delay chains through software rather than hardware.

The design also makes use of the half-rate registers.  As discussed, there currently are some obstacles in implementing these, so there is a simple parameter to bypass them.

Programmable_IOE_Delay_Chain_Interface.jpg (Click here for image)

 File:Programmable Delay Chain

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Last update:
‎06-27-2019 12:34 AM
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