This example illustrates how quickly and easily the Programmable Master component along with the System Console environment can be assembled into a test platform for memory interface analysis and testing.
The test platform for this example is the NEEK development board.
The DDR SDRAM on the NEEK board is the example memory interface described in the example.
The test system, as well as all of the test scripts for System Console, is published with this example.
pm_neek_ddr_analysis.pdf - this is the main documentation of the example.
hw_project.zip - this is an archive of the Quartus II project that was used to create the example.
README.TXT - contains instructions on how you can bring up the system in hw_project.zip on your own NEEK board.
The Programmable Master NEEK DDR Analysis Example System
This system is virtually identical to the simple examples provided with the Programmable Master component; however, this system uses the HP DDR controller core in place of an onchip memory. Many new scipts are added to this example to provide aditional interaction with the DDR memory interface.