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Programmable Master

Programmable Master

Latest Release

Release 9.1 can now be downloaded.

Overview

  • The Programmable Master is a configurable test master that allows you to create virtually any type of Avalon Memory Mapped master, pipelined, non-pipelined, bursting, non-bursting, etc.
  • The Programmable Master is delivered as an SOPC Builder component, and is intended to be integrated into SOPC Builder systems.
  • The primary use model is envisioned to be an SOPC system containing the Programmable Master which is controlled from a host workstation using the System Console infrastructure over the JTAG interface.
  • Using System Console you can write TCL scripts which load test vectors into the Programmable Master and command it to execute them, and then monitor various statistics that the master collects during execution.
  • The Programmable Master may be used in hardware deployed FPGA designs, or HDL simulation models along with the System Console infrastructure.
  • The advantage that the Programmable Master brings to system checkout and architectural verification is the simple fact that it can be configured to look like any legal master topology, and it has the ability to run test vectors at system speed. Test vectors will execute back to back as fastas the system interconnect fabric can accept them. So unlike a soft CPU or DMA controller which have predetermined constraints which they must conform to, the Programmable Master is basically unconstrained by any prerequisites, and may issue any type of data access patterns into the fabric from any type of master interface topology.
  • The Programmable Master can issue read and write transactions into the fabric.
  • Returning read data may be captured by the master, or compared against programmed vectors to detect read errors or unexpected read results.
  • Vectors may be programmed in such a way that the master executesthem one time, or loop indices may be configured to allow the master to loop thru the vectors over andover again.
  • Internal counters allow you to capture how long it takes for a sequence of vectors to execute, or count how many loops the vectors have looped thru. This allows you to derive performance metrics for how a master is actually performing in a given system environment.
  • An externally available input allows you to start and pause the master from an external signal source. This is useful for coordinating the actions of multiple Programmable Masters in a system.
  • A library of TCL scripts is provided along with the ProgrammableMaster to illustrate how one might control and interact with the component thru the System Console environment.

Download the Component

You can download the [[media:pm_release_91.zip}release 9.1 Programmable Master component]]. The component archive contains the SOPC Builder component, example TCL scripts to interact with it from System Console, and a PDF documentation file.

This is what the release 1.0 component GUI looks like:

Pm_gui.jpg (Click here for image)


Download examples that run on the NEEK

Download the Programmable Master example systems archive (not updated since 1.0). This archive contains a "readme.txt" file that contains directions on how to try these systems out on a NEEK development board. This archive contains two systems created to run on the NEEK board, one with a 32-bit Programmable Master and one with a 256-bit Programmable Master. Both systems connect the Programmable Master to a similar width onchip RAM, and contain a JTAG Master to interact and control the Programmable Master. The provided TCL scripts for the Programmable Master allow you to run simple test scripts on this example system System Console.

The example system is rather simple, and it looks like this:

Sopc_system.jpg.jpg (Click here for image)


Additional Programmable Master Examples

Programmable Master NEEK DDR Analysis Example - This example shows how to use the Programmable Master to analyse and test the DDR memory interface on a NEEK develpment board.

Release Notes

  • Version 1.0 - Initial Release
  • Version 9.0.0 - Programmable Master release 9.0.0 contains no functional or operational changes to the component, only some minor alterations were made to the hw.tcl script to accommodate some new validation checks that SOPC Builder was now making in release 9.0. In addition a few new user scripts were added to provide some pre-tested commands to interact with 64-bit and 128-bit implementations of the programmable master. Previously only 32-bit and 256-bit script examples were provided.
  • 'Version 9.1 - Programmable Master release 9.1 contains no functional or operational changes to the component, only some minor alterations were made to the hw.tcl script to accommodate some new validation checks that SOPC Builder now makes in release 9.1. In addition, some minor alterations were made to the pm_discovery_procs.tcl, some regular expressions were updated to match the output in 9.1 and the EXE extention was removed from application invocations within the script.

Download

§ pm_example_systems.zip

§ pm_release_10.zip

§ pm_release_90.zip - Release 9.0.0 of the component for Quartus II 9.0 compatibility.

§ pm_release_91.zip

Version history
Revision #:
1 of 1
Last update:
‎06-27-2019 12:33 AM
Updated by:
 
Contributors