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This guide will provide you with a step-by-step introduction on how to build your own FPGA design, compile, run, and debug the SW contained in the ARM core of the FPGA. It utilizes the bare metal HW Libs example design as a case for demonstrating single-step, cross-triggering between DS-5 and SignalTap, and trace. Although this example utilizes bare metal, it can quite easily be extended to any OS as well, such as Yocto Linux.
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For more complete information about compiler optimizations, see our Optimization Notice.