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RLDRAM 3 Main Page

RLDRAM 3 Main Page



Introduction

RLDRAM 3 stands for Reduced Latency DRAM 3 and is based on standard DRAM array architecture. RLDRAM 3 enables a faster, more efficient transfer of data by doubling performance and reduced latency compared to RLDRAMII. RLDRAM 3 memory is suitable for operation in which high bandwidth and deterministic performance is critical. 

The high performance of RLDRAM is achieved by very low random access delay (tRC), low data bus-turn around delay, simple command protocol and large number of banks . Hence RLDRAM 3 is optimized to meet the needs of high-bandwidth networking applications. There are 16 banks in RLDRAM 3. RLDRAM 3 is offered in an 18 and 36-bit bus. The extra bit per byte is used to support ECC.

RLDRAM 3 devices support the 1.2V HSTL I/O Standard. You can use this I/O Standard to interface with Altera FPGAs. RLDRAM 3 also supports both CIO and SIO, but Altera only supports CIO (Just like in RLDRAM II).


Supporting Documents

Altera RLDRAM 3 PHY + Northwest Logic Controller Solution Details

Integration guidance for RLDRAM 3 PHY with your controller

Version history
Revision #:
1 of 1
Last update:
‎06-27-2019 01:05 AM
Updated by:
 
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