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RapidIO Example Design

RapidIO Example Design



This example is RapidIO in Qsys to show how easy to build RapidIO system in Embedded system build tool, Qsys. User can build RapidIO system in a day without writing a lot of complicated connections. Overview 

To use the supplied design example, you will need a Cyclone V GX development kit, an Arria V starter kit or a Stratix V development kit. 

Block Diagram

 RapidioDE.png (Click here for image)

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RapidIO I IP 

Cyclone V GX (2.5Gbps x1 lane) Quartus II ver13.0sp1 

Arria V GX (2.5Gbps x1 lane) Quartus II ver13.1 

Stratix V GX (2.5Gbps x1 lane) Quartus II ver13.1 

RapidIO II IP 

Cyclone V GX (3.125Gbps x1 lane) Quartus II ver13.1: 

Arria V GX (3.125Gbps x1 lane) Quartus II ver13.1 

Stratix V GX (3.125Gbps x1 lane) Quartus II ver13.1 

Disclaimer

© 2013 Altera Corporation. The material in this wiki page or document is provided AS-IS and is not supported by Altera Corporation. Use the material in this document at your own risk; it might be, for example, objectionable, misleading or inaccurate.

Version history
Revision #:
1 of 1
Last update:
‎06-27-2019 01:07 AM
Updated by:
 
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