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Reading EDCRC EMR with User Logic Reference Design

Reading EDCRC EMR with User Logic Reference Design

This reference design accompanies Application Note AN539. It shows how to read the Error Message Register (EMR) via user logic. The EMR contains information regarding Error Detection CRC (EDCRC) errors found during a scan of the FPGA's configuration RAM (CRAM).

The reference design was developed on the Stratix V GX Devevelopment Kit. It uses the Stratix V internal oscillator to clock the control block. No device pins are used in this design; signals are observed using the Quartus II Signal Tap tool (configured with the file stp1.stp). Use Signaltap to observe internal signal activity after injecting a fault to the fault injection register as described in Application Note AN539.

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Last update:
‎06-26-2019 10:19 PM
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