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Altera Transceiver PHY IP Core User Guide (PDF)
Altera Stratix V Device Documentation
Altera Avalon Memory-Mapped Interface Specification (PDF)
Altera Reconfig Design File (ZIP)
The table below lists the specifications for this design:
This design implements the following blocks:
The attached zip file has all the required design and simulation files. To start the simulation, launch Modelsim and source phy_sim_top.tcl
Stratix V, Custom PHY IP, Tranceiver Reconfiguration Controller
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For more complete information about compiler optimizations, see our Optimization Notice.