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Reconfig Design Example 1

Reconfig Design Example 1



Contents

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External Links

Altera Transceiver PHY IP Core User Guide (PDF) 

Altera Stratix V Device Documentation

Altera Avalon Memory-Mapped Interface Specification (PDF)

Altera Reconfig Design File (ZIP) 


Design Specifications

The table below lists the specifications for this design:  

AttributeSpecification
Device FamilyStratix V GX
FPGA5SGXMA7K2F40C2
Quartus versionQuartusII v11.0, b157
Modelsim versionModelsim SE v6.6d
Datarate3.125Gbps
Data patternPRBS 23
Number of channels
IP usedCustom PHY IP, Traceiver Reconfiguration Controller

 

Design Overview

This design implements the following blocks:

  1. Custom PHY IP
  2. Transceiver Reconfiguration Controller
  3. PRBS Generator
  4. PRBS Checker
  5. Avalon Memory-Mapped (MM) Master


Simulation Guidelines

The attached zip file has all the required design and simulation files. To start the simulation, launch Modelsim and source phy_sim_top.tcl



Update History

  1. Initial Release - May 05 2011 


 See Also

  1.  Transceiver design examples 

 

Key Words

Stratix V, Custom PHY IP, Tranceiver Reconfiguration Controller 


   

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Version history
Revision #:
1 of 1
Last update:
‎06-26-2019 10:20 PM
Updated by:
 
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