Community
cancel
Showing results for 
Search instead for 
Did you mean: 

Reference Design - Altera Interlaken IP Throughput Measurement - Stratix GX/GT

Reference Design - Altera Interlaken IP Throughput Measurement - Stratix GX/GT



Interlaken MegaCore Function User Guide (PDF)External Links

Altera Avalon Memory-Mapped Interface Specification (PDF)


Design File

Altera Interlaken IP Throughput Measurement Reference Design for Stratix Devices (ZIP) 

Altera Interlaken IP Throughput Measurement Reference Design for Stratix Devices (PDF) 

Interlaken MegaCore Function Parameter Selection Worksheet (PDF) 



Design Specifications

The table below lists the specifications for this design:  

AttributeSpecification
Device FamilyStratix GX GT
Quartus versionQuartusII v11.1
Modelsim versionModelsim SE v6.6d
Number of Lanes and Data rate20Lane@6.375Gbps
Number of channels20
IP usedInterlaken IP

 

Design Overview

This design implements the following blocks:

This application note describes a reference design that demonstrates Altera Interlaken IP throughput measurement for various size packets. It also provides a design example to demonstrate integrating the Interlaken IP core in user applications. The Interlaken IP variant in this reference design is configured with 20 lanes at 6.375 Gbps, providing a real time hardware environment to measure throughput for a 100G Ethernet packet application. A companion Microsoft Excel worksheet that is provided with the reference design calculates throughput for applications that use other Interlaken IP configurations. The worksheet provides throughput and user side clock frequencies for various transceiver configurations using different numbers of lanes and different line rates.

Reference Design Guidelines

The attached zip file has all the required design and documentation files. 


This reference design offers the following features:

• The reference design uses internal loopback, to support transceiver channels that are not available for external loopback on the demonstration board.

• The reference design includes HDL code for supporting modules that you can reuse in your own design, such as a packet generator, a packet checker, a statistics keeper, and a performance meter, in addition to the Interlaken IP core.

• The design is easily modified for applications that use different Interlaken IP core variations.

• The design includes an embedded Qsys control unit using a Nios-II microprocessor, which enables users to configure, control, and retrieve status and performance information interactively from a PC through a USB connection. 

• The design provides a reconfigurable packet generator to dynamically change traffic patterns.

• The current reference design targets an Altera Stratix IV GT device.


This reference design demonstrates the following Altera technology:

• Interlaken IP core and its throughput performance

• Stratix IV GT devices

• Qsys system integration tool

• Nios II microprocessor

Update History

  1. Initial Release - Feb 24 2012 


 

Key Words

Stratix IV, Stratix V, Interlaken IP, Throughput, Bandwidth 


   

© 2010 Altera Corporation. The material in this wiki page or document is provided AS-IS and is not

supported by Altera Corporation. Use the material in this document at your own risk; it might be, for example, objectionable,

misleading or inaccurate.Retrieved from http://www.alterawiki.com/wiki/Altera_Wiki

Version history
Revision #:
1 of 1
Last update:
‎06-26-2019 10:32 PM
Updated by:
 
Contributors