The table below lists the specifications for this design:
Stratix GX GT
Modelsim SE v6.6d
Number of Lanes and Data rate
Number of channels
This design implements the following blocks:
This application note describes a reference design that demonstrates Altera Interlaken IP throughput measurement for various size packets. It also provides a design example to demonstrate integrating the Interlaken IP core in user applications. The Interlaken IP variant in this reference design is configured with 20 lanes at 6.375 Gbps, providing a real time hardware environment to measure throughput for a 100G Ethernet packet application. A companion Microsoft Excel worksheet that is provided with the reference design calculates throughput for applications that use other Interlaken IP configurations. The worksheet provides throughput and user side clock frequencies for various transceiver configurations using different numbers of lanes and different line rates.
Reference Design Guidelines
The attached zip file has all the required design and documentation files.
This reference design offers the following features:
• The reference design uses internal loopback, to support transceiver channels that are not available for external loopback on the demonstration board.
• The reference design includes HDL code for supporting modules that you can reuse in your own design, such as a packet generator, a packet checker, a statistics keeper, and a performance meter, in addition to the Interlaken IP core.
• The design is easily modified for applications that use different Interlaken IP core variations.
• The design includes an embedded Qsys control unit using a Nios-II microprocessor, which enables users to configure, control, and retrieve status and performance information interactively from a PC through a USB connection.
• The design provides a reconfigurable packet generator to dynamically change traffic patterns.
• The current reference design targets an Altera Stratix IV GT device.
This reference design demonstrates the following Altera technology:
• Interlaken IP core and its throughput performance
• Stratix IV GT devices
• Qsys system integration tool
• Nios II microprocessor
Initial Release - Feb 24 2012
Stratix IV, Stratix V, Interlaken IP, Throughput, Bandwidth