cancel
Showing results for 
Search instead for 
Did you mean: 
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
830 Discussions

Reference Design - Arria V Hard Memory Controller Bonding Interface

Reference Design - Arria V Hard Memory Controller Bonding Interface




Initial Release – June 2012 – Arria V DDR3 SDRAM x32 480 MHz, Quartus II v12.0, DDR3 SDRAM Controller with UniPHY.

Last Major Update

 

Introduction

Hard memory controller (HMC) in Arria V and Cyclone V devices offer bonding features to bond two single HMCs. This allows two ports to be used to service a single bandwidth stream and also provide flexiblity to expand the interface data width. For example, you can bond two 32-bit HMCs to form a 64-bit interface.


Bonding Interface Requirement

You can only bond two HMCs with same memory configuration (same frequency, same timing parameters etc). However, you still can bond two HMCs with same memory configuration with different data width. For example, you can bond a single 16-bit HMC with another 32-bit HMC to form a 48-bit interface provided both HMCs are same memory configurations.


Design Overview

This design demonstrates how to bond two 450MHz DDR3 SDRAM 32-bit UniPHY hard memory controllers to form a 450MHz 64-bit DDR3 SDRAM interface with a single master on Arria V FPGA. Same bonding guidelines is applicable to Cyclone V hard memory controller. This design is generated in Qsys flow. Simulation model and test bench generated by Qsys will be used to validate the functionality of the bonded hard memory controllers through simulation. Figure below shows the block diagram of this reference design.



BondingInterface.png (Click here for image)



Design Specifications

The table below lists the specifications for this design:

AttributeSpecification
Quartus versionQuartusII v12.0
Modelsim Altera version10.0d
FPGA5AGXFB3H6F35C6
Memory deviceDDR3 SDRAM (JEDEC DDR3-1066E 1GB x8)
Memory speed533MHz
Memory topologyx32-bit, Component
IP usedDDR3 SDRAM Controller II with UniPHY IP 

 

Design Files

Design files are located in this zip file - AV_DDR3_HMC_BondingDesign. There are three main folders in this design which located in the HMC folder.


1) Synthesis - Consists of all the design files for synthesis and compilation. 

2) Simulation - Consists of design files for simulation.

3) Testbench - Consists of complete full system test bench design files for RTL simulation.


Design Generation Step

 This reference design is created in the Qsys flow. 

DDR3 SDRAM UniPHY Hard Memory Controller 


'1. Generate a DDR3 SDRAM Controller with UniPHY

  1. Add DDR3 SDRAM Controller with UniPHY from the component library panel under Memories and Memory Controller category
  2. Enable Hard External Memory Interface under Interface Type in DDR3 SDRAM Controller with UniPHY GUI


'2. Set parameters for Memory Controller with UniHY'

• PHY Settings Tab

  1.  Select JEDEC DDR3 -1066E 1GB X8
  2.  Set Speed grade to 6.
  3.  Set Memory clock frequency to 450 MHz
  4.  Set PLL reference clock frequency to 125 MHz.
  5.  Select Full for rate on Avalon-MM interface.

• Memory Parameters Tab

  1.  Type 32 for Total interface width.
  2.  Select 1 for Number of slots and Number of chip select per slot, select 1.
  3.  Select 1 for Number of clocks per chip select.
  4.  Type 14 for Row address width.
  5.  Type 10 for Column address width.
  6.  Type 3 for Bank address width.
  7.  Select Sequential for Read Burst Type under Memory Initialization Options,
  8.  Select DLL off for DLL precharge power down
  9.  Select 7 for Memory CAS latency setting ,
  10.  Select RZQ/6 for Output drive strength setting.
  11.  Select Disabled for Memory additive CAS latency setting.
  12.  Select ODT Disabled for ODT Rtt nominal value. You may enable the ODT to improve the signal integrity
  13.  Select Manual for Auto selfrefresh method
  14.  Select Normal for Selfreferesh temperature
  15.  Select 6 for Memory write CAS latency setting
  16.  Select Dynamic ODT off for Dynamic ODT(Rtt_WR) setting. 

• Board Settings Tab 

 This design uses default board settings. Users should do board simulation for proper values in this page. 


• Controller Settings Tab 

  1.  Enable Generate power-of-2 data bus widths for Qsys or SOPC builder
  2.  Set 4 for Maximum Avalon-MM burst length under Avalon Interface
  3.  Enable Export bonding interface under Multiple Port Front End (MPFE) to export the bonding interface port
  4.  Select 1 for Number of ports
  5.  Select Bidirectional in port type
  6.  Select 64 for port width

To achieve optimum efficiency it is recommended to set the MPFE data port width according to calculation below:

     2* (frequency ratio of HMC to user logic) * Interface data width 

For example, if the user logic frequency is half of the HMC frequency, set the port width 4x of the interface data width. If the frequency ratio of HMC to user logic is a fractional value, use higher number. For example, the frequency ratio is 1.5, then use 2.


• Diagnostics Tab

  1.  Select Skip calibration for Auto-calibration mode to reduce the simulation time.
  2.  Enable Skip Memory Initialization Delays to reduce the simulation time.
  3.  Enable verbose memory model output to print out the simulation activities in the transcript for better debugging. 


3. Repeat steps 1 and 2 above for the second x32-bit UniPHY hard memory controller.

4. Once two identical hard memory controllers are generated, connect the bonding_in and bonding_out port for both controllers as shown in figure below.


Bondingports.png (Click here for image)



Bonding Bridge

Bonding bridge is a manually added new component in Qsys component library in this design. The function of this block is to process two sets of avalon signals from two bonded hard memory controllers to the single master (pattern generator). This is to allow single master to control two controllers. Below is the process of the bonding bridge block:

- AND both avl_ready signals from both HMCs before going into the pattern generator

- AND both avl_rdata_valid signals from both HMC before going into the pattern generator

- Branch following signals below from pattern generator to both HMCs

  Avl_burstbegin

  Avl_addr

  Avl_read_req

  Avl_write_req

  Avl_size

- Split the signals below according to each HMC MPFE data port width

  Avl_rdata

  Avl_wdata

  Avl_be

Bonding bridge is predesign for this design (BondingBridge.v). It is included in the Qsys Component Library, under Project section, in the Bridges category. Add this component into the design.

Note: The avalon address width in the bonding bridge block is larger than the avalon address width in HMCs is for mapping the btye addressing to word addressing.


Pattern Generator

1. Generate Pattern Generator

Add Pattern Generator from the component library panel under Memories and Memory Controller category


2. Set parameters for Pattern Generator

• Interface Settings

  1. Set 128 for Avalon Data Width. Sum of two HMCs avalon data width.
  2. Set 8 for Avalon Symbol Width
  3. Enable Generate power-of-2 data bus widths for Qsys or SOPC builder
  4. Set 28 for Avalon Address Width
  5. Enable Generate per byte address
  6. Enable Generate Avalon-MM begin burst transfer signal
  7. Set 4 for Maximum Avalon-MM burst length
  8. Enable Generate the per-bit pass/fail signals in the status interface

• Traffic Settings

  1. Set 1 for Number of loops through patterns to reduce the simulation time.
  2. Enable data comparison
  3. Use default setting for the remaining settings

PLL

This PLL is used to provide 125MHz clock to pattern generator, bonding bridge, hard memory controller MPFE address command and data ports. 

• Generate PLL

 Add Altera PLL from the component library panel under PLL category

• Set parameters for Altera PLL

  1. Set 6_H6 for Device Speed Grade
  2. Set 125.0MHz for Reference Clock Frequency
  3. Set 1 for Number of Clocks
  4. Set 125.0 MHz for Desired Frequency under outclk0


Connections and Generation

1. Connect the blocks as shown in the diagram below:


HMCQsysConnection.png (Click here for image)



2. Save the design as HMC.sys

• Generation tab

  1. Select Verilog for Create Simulation model
  2. Select Simple, BFMs for clocks and resets for Create testbench Qsys system
  3. Select Verilog for Create testbench simulation model
  4.  Enable Create HDL design files for synthesis
  5. Enable Create block symbol file (.bsf)

3. Click Generate to generate the design


Design Analysis 


1. Set Top-Level Entity

The Qsys generates the whole bonding interface system synthesis files for analysis. Those files are located in the synthesis folder.

  1. Go to Assignment -> Files
  2. Add in the HMC.qip and HMC.v file 
  3. Set the HMC.v file as top level entivity


2. Perform Analysis and Synthesis 

This step is required so Quartus can determine the names of the external ports connected to the UniPHY for when the I/O assignments are created in the next step.


3. Assign the pin and DQ group settings 

Run the tcl script HMC_mem_if_ddr3_emif_0_p0_assignments.tcl to assign the pin and DQ group assignments. This tcl script is generated for you by the IP megawizard 

• Verify in the Assignment Editor that pin assignments have been created successfully 


4. Define core clock in the sdc file

Since the core logic is driven by another PLL, hence we need to manually define the core clock in the sdc file

  1. Open the HMC_mem_if_ddr3_emif_0_p0.sdc file which located in the submodules folder in the synthesis folder
  2. Look for this command "set pll_driver_core_clock $pins(pll_driver_core_clock)"
  3. Replace "$pins(pll_driver_core_clock)" with the core clock"pll_0|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk"

The new command looks like this " set pll_driver_core_clock "pll_0|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk" "

Note: You will find Quartus II report critical warning as below because the core logic is driven by another PLL:

          Critical Warning: <variable'_name>_pin_map.tcl: Failed to find PLL clock for pins

     To get rid of this critical warning, replace line below in HMC_mem_if_ddr3_emif_0_p0_pin_map.tcl

      from

              if {[get_collection_size [get_registers -nowarn $pins(driver_core_ck_pins)]] > 0} {

       to    

              if {[string compare -nocase $pins(driver_core_ck_pins) ""] != 0 && [get_collection_size [get_registers -nowarn $pins(driver_core_ck_pins)]] > 0} {


5. Do a Full Compile

This should take about 10 minutes depending on the compiling PC.


6. Timing Analysis results 

• In the Compilation Report, Time Quest Timing Analyzer folder expand the three VT model folders, and the Report DDR folder

- Check the summary at the bottom of that report

- Check that all set up and hold timings pass


  


Design Simulation


The Quartus II software creates a complete simulation test bench for functional simulation in the testbench folder. To run the RTL simulation, perform the following steps:


• Open Modelsim. 

• Move into the directory ./HMC/testbench/mentor

• Run "Source msim_setup.tcl" in the console

• Run "dev_com" 

• Run "com"

• Run "elab"

• Run "do wave.do" to load the predefined waveform

• Run "run -all" 

• Observe the results in the ModelSim Wave window. Monitor the test_complete, pass, fail and pnf_per_bit signals.


Notes/Comments


Update History

Initial Release – June 2012 – Arria V DDR3 SDRAM x32 480 MHz, Quartus II v12.0, DDR3 SDRAM Controller with UniPHY.

 

See Also

1. List of designs using Altera External Memory IP 


External Links

1. Altera's External Memory Interface Solutions Center 

2. Altera's External Memory Interface Handbook 

 

Key Words

UniPHY, DDR3 SDRAM, Reference Design, External Memory , Arria V, AV, Cyclone V, CV, Hard Memory Controller, HMC, Bonding Interface

Version history
Revision #:
1 of 1
Last update:
‎06-26-2019 10:34 PM
Updated by:
 
Contributors