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Reference Design : Gen2x8 PCIe IP Core - Stratix V (without Qsys)

Reference Design : Gen2x8 PCIe IP Core - Stratix V (without Qsys)

The purpose of this page is to provide a link to the user, where the user can download the Stratix V Gen2 x8 AVST DMA reference design without having Qsys.



  • Fast and easy to develop high performance PCIe Gen2x4 hardware with AVST DMA IP for ACDS revision 14.1.0B186 or later
  • Completed Quartus reference design is in the attached zipped file, which provides a pre-configured Qsys system

Allows the user to modify the Qsys file and re-generate the design

  • Includes Linux driver and application that works with the reference design
  • Use built in AVMM DMA IP to transfer data between the on-chip memory in the FPGA and the system memory
  • Support infinite loop to test the system and the IP stability
  • For each loop, all transferred data are compared with data in the source location to guarantee data integrity


  • Quartus II version 14.1.0 build 186
  • A PC provides a PCI Express Gen2 x8 slot

This reference design has been tested with Intel Sandy Bridge

  • The attached reference design

The SOF is available in the folder pcie_quartus_files as top.sof

  • Altera PCI Express Stratix V Devkit with FPGA 5SGXEA7K2F40C2

Refer to the link for details

  • A system with 64-bit Windows 7 installed

Design Block Diagram

Design Block Diagram- AN456.png (Click here for image)

How to run the application

This design is similar as the Stratix V gen2x8 AVST reference design in AN456 PCI Express High Performance Reference Design

Please follow the guide from AN456 to perform the hardware, software installation and run the reference design.

How to create the PCIe design without Qsys

This design is created without using Qsys file.

It consists of

  1. DUT - SV gen2x8 IP core
  2. Apps - Application logic to perform read and write DMA
  3. Reset controller
  4. Reconfig driver and Transceiver Reconfiguration Controller IP.

In order to create another PCIe design without Qsys, you need to

  1. Generate the PCIe IP core and Transceiver Reconfiguration Controller IP through IP Catalog.
  2. Apply the application logic, reset controller and reconfig driver into your design. (you may copy these modules from design below)
  3. Interconnect all the modules by referring to design below
  4. Compile and run in your hardware


Link to download the project File:S5gx x8 g2 ast128 5SGXEA7K2F40 141 IPcore.qar


July 16, 2015 - Created this page

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Last update:
‎06-26-2019 10:52 PM
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