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Reference Design: Gen3 x8 AVMM 256-bit DMA for External DDR3 - Stratix V

Reference Design: Gen3 x8 AVMM 256-bit DMA for External DDR3 - Stratix V



The purpose of this page is to provide a link to the user, where the user can download the Stratix V Gen3 x8 AVMM DMA for external DDR3 reference design. For the DMA details, refer to the reference documentation section below.

Overview

Features

  • Fast and easy to develop high performance PCIe Gen3x8 hardware
  • Example system is in the attached zip file, which provides a pre-configured Qsys system
  • Includes both 64-bit Windows and Linux driver and application that works with the example design
  • Targets Altera Stratix V GX PCIe DevKit, so the user can program the included SOF into the FPGA directly
  • Demonstrate the DMA to transfer data back and forth between the system memory and the external 128MB DDR3 memory on the DevKit

Requirements

Software

  • ACDS 13.1 or later
  • A Linux system with Kernel 2.6.32-358 or later
  • 64-bit Windows 7

Hardware

  • Stratix V GX PCIe DevKit
  • Altera USB Blaster to program the FPGA


Reference Documentation

Refer to the document for details File:Avmm 256 dma gen3x8.pdf


Validations

The attached reference design has been tested in multiple Linux platform with different chipsets. 

64-bit Windows 7 The Linux OS includes

  • 32-bit Ubunto
  • 32-bit and 64-bit CentOS 6.4
  • 64-bit Redhat

The chipset include

  • PCIe Gen3 Sandybridge
  • PCIe Gen3 Ivybridge


Limitations

Since the design is still preliminary version, so it has some limitations

  1. The performance number highly depends on the system it is testing with. The limitation is not due to the DMA engine or the PCIe HIP, it depends on how fast the root complex returns the data to the DMA. Hence, you may not be able to get the performance number listed above.
  2. The QSYS file in the reference design below is not able to generate the simulation test bench. If simulation is needed, please contact factory.
  3. The design was generated by the pre 14.0 ACDS, hence the IP can't be re-generated in 13.1 Qsys. If modification and re-generation is needed, please refer the steps below about how to generate the IP in 13.1 ACDS.
  4. The on board DDR3 is a single ported memory. Therefore, it is not capable to service simultaneous read and write generated by the DMA effectively. Lower performance number for simultaneous test is expected. Hence, it is not a good reference design to show the real performance of the DMA and the hard PCIe IP for simultaneous operation. To get the real performance for simultaneous operation, use another Stratix V AVMM DMA design in Wiki, which uses a dual ported on chip memory instead of the single ported external DDR3


How to Regenerate the IP in ACDS 13.1

To generate and compile the IP in ACDS 13.1, please do the following steps

  1. Unzip the file, File:Altera pcie hip 256 avmm 14.0c rev3.zip
  2. Copy all unzipped folders and files into the folder \ip\altera\altera_pcie\altera_pcie_hip_256_avmm\ under Quartus installation folder. Overwrite the original folders and files there.

After that, the Qsys file in the reference design can be opened, changed, and re-generated in ACDS 13.1


Link to the software and reference design

Revision 1 - Quartus 14.0

Reference design: File:SV AVMM DMA DDR3 128M.zip

Linux driver and application: File:SV AVMM DMA DDR3 128M Apps.tar.gz. To run this application, must use Linux Kernel 2.6.32-358 or above, such as CentOS 6.4 or later.

64-bit Windows driver and application:File:Gui package 090 80000000.zip. In the package, there is a word document which explains how to install the driver, what additional software needed to be installed, and how to run the application.

Revision 2 - Quartus 15.1.2

Reference design: File:Hip svgx g3x8 avmm dma256 ddr3 15 1 2.qar

Linux driver and application: File:SV AVMM DMA DDR3 128M Apps.tar.gz. To run this application, must use Linux Kernel 2.6.32-358 or above, such as CentOS 6.4 or later.

64-bit Windows driver and application:File:Gui package 090 80000000.zip. In the package, there is a word document which explains how to install the driver, what additional software needed to be installed, and how to run the application.


Disclaimer

The use of the material on this page is governed by, and subject to, the terms and conditions of the Altera Program License Subscription Agreement, the Altera MegaCore Function License Terms and Conditions, and the Altera Hardware Reference Design License Agreement respectively.

Version history
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Last update:
‎06-26-2019 10:26 PM
Updated by:
 
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