(Redirected from Stratix V Gen3 x8 Avalon-ST 256-bit Reference Design)
This article provides a Stratix GX V PCIe Gen3 x8 reference design, targets Altera Stratix V GX Development Kit. The project contains the compiled image which can be programmed into the FPGA on the Development board directly. Any user can use it as a reference when they develop their own PCIe Gen3 x8 design. In this reference design, a high performance DMA is in the application layer, it can be used to show the performance of the PCIe HIP Altera provided. The article explains the architecture of the whole design, how the DMA is used, and its limitation.
The reference design includes the following components
The reference design consists of the following components:
The TLP Blaster DMA example consists of two DMA modules which can support DMA read and write transaction. The DMA write module implements the write operation by transfer data from the application layer to the system memory across the PCIe link. The DMA read module implements the read operation by transfer data from the system memory to the application layer across the PCIe link. The DMA module does not store any file data. Instead, it contains a pattern generator for the DMA write payload. For the read back data, the DMA does not do any checking.
The reference design uses the following directory structure:
This section describes how to install the reference design for hardware and how to run the software application.
The reference design requires the following hardware:
To be able to run the included application, the following softwares are required.
Plug the Stratix V GX card into a PCIe slot in the first computer, where you are going to run the application to show the throughput. Power up the Development board by either external power supply included in the Development Kit package or motherboard, then download the SOF into the FPGA through the USB Blaster. If the Development board is powered by the motherboard slot, then a reboot is needed after the FPGA is programmed. It allows the system BIOS to enumerate the FPGA.
You must have the Administrator privileges to install the software application. The reference design includes two software applications, one is for 32-bit Windows, another one is for 64-bit Windows. Perform the following steps to install the application and the associated driver
Perform the following steps to run the application.
What the application will do are
Except using the included applications to run the DMA in the real hardware on bench, the user can also run the simulation to show the performance. A completed simulation environment can be downloaded from a separated link below. The DMA write and read simulus are included. Both write and read performance numbers are reported at the end of the simulation. For now, ModelSim simulation is supported.
Not all designs support simulation.
The reference design package includes a QSYS file, it allows you to re-generate the whole project by QSYS in Quartus. However, if you re-generate the project in QSYS, the TLP Blaster DMA module will be removed, you won't be able to run the TLP Blaster in the new project you generated no matter in simulation or in real hardware.
If you really need to modify the QSYS and re-generate the IP, then you can follow the steps below for putting the TLP Blaster design back into the new project.
1. Use a Stratix V Gen3 x8 design which already has TLP Blaster in, for example, download the design here.
2. Save the file altpcied_sv_hwtcl.sv in folder testbench/top_tb/simulation/submodules or the folder where the synthesis files located.
3. Modified the included QSYS file and re-generate all IPs. The device ID in the HIP should be 0xE002, otherwise, the software won't be able to run.
4. Copy new generated files to the folder where the synthesis files located.
5. Copy the original altpcied_sv_hwtcl.sv file back to the folder where the synthesis files located, replace the new generated file.
6. Re-compile the design
The following is the link where you can download the reference design.
Quartus 12.1 design File:Top g3 x8.qar
Quartus 13.0sp1 design File:Hip s5gx x8 g3 ast256 13 0sp1.qar
Quartus 13.1 design File:Hip s5gx x8 g3 ast256 13.1.qar
Quartus 13.1 simulation testbench File:Testbench g3x8 13.1.zip
Quartus 14.0 design
Quartus 14.1 design
To run the application, the user must run a Command Prompt as Administrator. In the Command Prompt, go to the "Install" folder and type in "install" to install the driver for the device. After that, run the application "g3dma_diag.exe" in the root folder.
Application and driver for 32-bit Windows File:Rel G3DMA x32.zip
Application and driver for 64-bit Windows File:Rel G3DMA x64.zip
The followings show the performance numbers by using the reference design. The performance numbers can vary dramatically in different systems due to other hardware's limitations.
In Intel Sandy Bridge Core i7 - 3930k CPU @3.2GHz.
Gen3 x8, Write: 6.9GB/s, Read: 6.9GB/s
Gen3 x4, Write: 3.5GB/s, Read: 3.5GB/s
Gen3 x1, Write: 870MB/s, Read: 880MB/s