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Reference Design - PCIe SRIOV - Stratix V

Reference Design - PCIe SRIOV - Stratix V



Overview

This page gives a reader an example design of creating a design with Altera PCIe SRIOV IP. The reference design was created by Qsys flow by Quartus II revision 14.0 or later.

Design Configuration

In the reference design, the IP is configured as

  • 1 physical function (PF), it requests 128KB memory by PCIe BAR0
  • 4 virtual functions (VF), it requests 64KB memory by PCIe BAR0. All VFs are assigned to the PF.

For the PCIe link, it supports PCIe Gen3 x8. In the IP, the internal bus width is 256-bit and run at 250MHz.

Block Diagram

The following shows the block diagram of the reference design.


SRIOV Reference Design Block Diagram- Sriov.PNG (Click here for image)


Files Included

The following files are included in the reference design

  • All RTL files needed to compile the project. Use can restore the QAR file and re-compile the design immediately. The files are located in folder top/synthesis/submodules.
  • The SOF file which targets Stratix V GX PCIe DevKit. The SOF file is located in folder pcie_quartus_files
  • The Qsys file which was used to create the project. The user can change the IP's configuration by changing the Qsys file, then re-generate a new project.

Download the reference design

Reference design created by Quartus II 14.0

File:Svgx sriov 1pf4vf 14 0.qar

History

August 11, 2014 - Page is created

Version history
Revision #:
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Last update:
‎06-26-2019 10:49 PM
Updated by:
 
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