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This page gives a reader an example design of creating a design with Altera PCIe SRIOV IP. The reference design was created by Qsys flow by Quartus II revision 14.0 or later.
In the reference design, the IP is configured as
For the PCIe link, it supports PCIe Gen3 x8. In the IP, the internal bus width is 256-bit and run at 250MHz.
The following shows the block diagram of the reference design.
SRIOV Reference Design Block Diagram- Sriov.PNG (Click here for image)
The following files are included in the reference design
Reference design created by Quartus II 14.0
File:Svgx sriov 1pf4vf 14 0.qar
August 11, 2014 - Page is created
For more complete information about compiler optimizations, see our Optimization Notice.