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Reference Design - Stratix V AVMM DMA

Reference Design - Stratix V AVMM DMA


The purpose of this page is to provide a link to the user, where the user can download the Stratix V Gen3 x8 and Gen3 x4 AVMM DMA reference design. For the DMA details, refer to the user guide below.


  • Fast and easy to develop high performance PCIe Gen3x8 and Gen3x4 hardware
  • Example system is in the attached Quartus archive, which provides a pre-configured Qsys system
  • Includes 64-bit Windows and Linux driver and application that works with the example design
  • Peak throughput (142 cycles of 256-bit @ 250MHz) at Gen3x8 design
  • 7.1 GB/s* : back to back Tx Memory Write 256 Byte payload
  • 7.0 GB/s* : back to back Rx Read Completion Throughput
  • Example design throughput averaged across 2 MBytes transfer with descriptors overhead
  • Read/Write : up to *6.4GB/sec* per direction
  • Simultaneous read/write : *11.4GB/sec*


  • Preliminary release in ACDS 13.0sp1

Optimized for better simultaneous read and write peroformance - increased by 30%

Fixed address alignment issue found in ACDS 13.0, any DW address alignment is acceptable

  • Example Design

Altera PCI Express Stratix V Devkit with 5SGXEA7K2F40C2

A system with either 32-bit or 64-bit Linux or 64-bit Windows 7 installed

User Guide

Refer to the document below for details

File:Avmm 256 dma gen3x8.pdf


The attached reference design has been tested in multiple Linux platform with different chipsets.

64-bit Windows 7

The Linux OS includes

  • 32-bit Ubuntu
  • 32-bit and 64-bit CentOS 6.4 and 6.5 with Kernel version 2.6.32 - 431
  • 64-bit Redhat

The chipset include

  • PCIe Gen3 Sandybridge
  • PCIe Gen3 Ivybridge


Since the design is still preliminary version, so it has some limitations

  1. The performance number highly depends on the system it is testing with. The limitation is not due to the DMA engine or the PCIe HIP, it depends on how fast the root complex returns the data to the DMA. Hence, you may not be able to get the performance number listed above.
  2. The QSYS file in the reference design below can't generate the simulation testbench. If simulation is needed, please contact factory.

Link to the software and reference design

Gen3 x8 256-bit Design

Revision 1

This revision has been obsoleted, please use next revision (revision 2) instead.

Revision 2

This revision has the following improvement when compared with revision 1

  1. It improves the performance for small transfer size, such as 64-byte transfer for each descriptor
  2. The application uses randomized data instead of incremental
  3. The application provides infinite loop for user

This revision has been obsoleted, please use next revision (revision 3) instead.

Revision 3

This revision has the following improvements when compared with revision 2 above

  1. Supports out of ordered completions
  2. Supports 1 DW transfer size of a descriptor
  3. Increases the on-chip memory size to 64KB
  4. The application supports the transfer size up to 1MB
  5. The application supports different number of descriptors, from 1 to 128

To generate and compile the IP in ACDS 13.1 or later version, please do the following steps

  1. Unzip the file, File:Altera pcie hip 256 avmm 14.0c
  2. Copy all unzipped folders and files into the folder \ip\altera\altera_pcie\altera_pcie_hip_256_avmm\ under Quartus installation folder. Overwrite the original folders and files there.

After that, the Qsys file in the reference design can be opened, changed, and re-generated in latest ACDS

Revision 4

This revision added in the special code in sub-systemID, so it can run with Windows GUI.

Link to the reference design : File:Avmm dma 256 rev4

Revision 5

Update the design to Quartus 15.1.2

Link to the reference design : File:PCIe SVGX AVMM DMA On Chip Mem 151.2.qar

Revision 6

Update the design to Quartus 16.0.2

Link to the reference design : File:PCIe SVGX AVMM DMA On Chip Mem

Gen3 x4 128-bit Design

Reference design: File:Avmm dma 128

Software Download


Revision 1

Link to download the application and driver File:Avmm dma linux.tar.gz

Revision 2

Link to download the application and driver File:Linux for AVMM DMA On Chip Mem.tar.gz

To run this application, must use Linux Kernel 2.6.32-358 or above, such as CentOS 6.4 or later.


Revision 1

64-bit Windows driver and application:File:Gui package 090

In the package, there is a word document which explains how to install the driver, what additional software needed to be installed, and how to run the application.

Other documents

This document provides the register map for revision 2 DMA - File:Avmm dma 140 v093.pdf


The use of the material on this page is governed by, and subject to, the terms and conditions of the Altera Program License Subscription Agreement, the Altera MegaCore Function License Terms and Conditions, and the Altera Hardware Reference Design License Agreement respectively.

Version history
Last update:
‎06-26-2019 10:48 PM
Updated by: