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The attached document describes different methodologies for duplicating registers to help with timing closure. Topics include:
- Why do registers with large fan-outs have worse timing(it's not due to loading)
- Physical Synthesis Register Duplication
- Max Fan-out
- Manual Logic Duplication
- Pros and cons of doing this in RTL or through assignments
- Analysis of a real design with various techniques(I have not attached the design, but have critical path screen-shots)
File: Register Duplication for Timing Closure.pdf
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