Remote System Update (RSU) example on BeMicro SDK using System Console

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Remote System Update (RSU) example on BeMicro SDK using System Console

Description

This page has been created to assist users that prefer to use logic for controlling the Remote System Update (RSU) feature using Cyclone III and Cyclone IV FPGAs. The example was verified using the BeMicro SDK evaluation board.

The example designs are based upon the following wiki page:

https://forums.intel.com/s/ics-frm-article/a3g0P0000005RSTQA2/remote-update-for-cyclone-v

However, the ALTREMOTE_UPDATE command structure for Cyclone III and Cyclone IV is significantly different than Cyclone V, so the system console tcl scripts were written to match Cyclone III and Cyclone IV. The command structure for addressing the ALTREMOTE_UPDATE function for Cyclone III and Cyclone IV can be found in the System Console tcl scripts within the FI project directory. The factory image (FI) and application image (AI) projects can be found in the download section below.

The example RSU test system consists of:

• A Factory Image (FI) that will be placed at address location 0x0 in the EPCS16
• An Application Image (AI) that will be placed at 0x100000 in the EPCS16
• The FI and AI are identical except for a HW_VERSION PIO register that is used to validate either the FI or AI image
• The RSU functionality is controlled via System Console, but can be extended to any other Avalon-MM Master, including NIOS

Items of Note

1. When using System Console, it is necessary to shift the addresses into the RSU component by two bit locations, in order to translate to word-addressing. When using NIOS, this is unnecessary when using IORD() and IOWR().
2. The ALTREMOTE_UPDATE Megafunction User Guide may state that the Boot Address / Page Select should be shifted down by 8 bits (i.e., the 32-bit register should hold the upper 24-bits of the desired boot address). Note that this is only true in the case of 256Mb configuration devices. No shift is necessary for devices that are 128Mb or smaller. https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd12052012_840.html
3. The boot address entered into the Write application boot address (read_source = 00b; param = 100b) is 0x40000 because it is operating on 4-byte boundaries. Thus, 0x40000 correlates to 0x100000 as the start address for the application image in the EPCS16.

Download

File:CycloneIV RSU BeMicroSDK System Console.zip

Note: it is also necessary to download the Qsys IP core below for the example design to operate properly. The Qsys IP core can then be applied to your specific application.

Cyclone IV Qsys core

To use this core, download from the link below, unzip, and place into your project ip directory. Open Qsys. You may need to add the new ip/rsu_cyclone4 directory in the Qsys IP search path. This core MUST run at a a clock lower or equal to 40 MHz.

File:Rsu cyclone4 SC.zip

This core can also be used for Cyclone III.

See Also

BeMicro SDK

Props

Special thanks to Cal and Shawn.