This is an example remote update core for Arria V, which is similar to the one for Cyclone III in Qsys. To use this core, create an ip/rsu dir in your project dir, and copy the attached files in it. Then you can add the core in Qsys. Driver is similar to Cyclone III.
This core MUST run at a clock lower or equal to 40 MHz.
RSU circuitry is the same for Cyclone V, Arria V, and Stratix V, so these downloads are nearly identical to the Cyclone V RSU files.
An example RSU test system is also included. This test system consists of:
A Factory Image (FI) that will be placed at 0x0 in the EPCS
An Application Image (AI) that will be placed at 0x450000 in the EPCS
The FI and AI are identical except for a HW_VERSION PIO register that is used to validate which image is current loaded
The RSU functionality is controlled via System Console, but can be extended to any other Avalon-MM Master, including Nios
Items of Note
When using System Console, it is necessary to shift the addresses into the RSU component by two bit locations, in order to translate to word-addressing. When using Nios, this is unnecessary when using IORD() and IOWR().
The altremote_update user guide may state that the Boot Address / Page Select should be shifted down by 8 bits (i.e., the 32-bit register should hold the upper 24-bits of the desired boot address). Note that this is only true in the case of 256Mb configuration devices. No shift is necessary for devices that are 128Mb or smaller. http://www.altera.com/support/kdb/solutions/rd12052012_840.html
The AnF bit MUST be set to 1 if you want to read the boot address from the application image. If AnF is not set to 1, then the boot address will always read back as 0x00000000.