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I'm seeing a lot of people still using this design. It's on here just in case you are using the SGDMA on the Quartus II installer; however, you should validate whether that SGDMA works for you or if you should be using the modular SGDMA that is located here:  Modular_SGDMA


The Scatter-Gather Direct Memory Access (SGDMA) design example illustrates how you can perform data transfers without processor overhead becoming a limiting factor. The SGDMA intellectual property (IP) is available for free in SOPC Builder and allows you to transfer between Avalon® memory-mapped and streaming interfaces. The main difference between the SGDMA and a regular DMA is that multiple transfers are handled by the hardware itself instead of by intervention from a host such as the Nios® II embedded processor. This typically reduces the downtime between transfers to a single clock cycle. Applications that typically benefit from using a SGDMA are networking, audio, and video processing.

The design example performs memory transfers between an external SSRAM memory component and on-chip FIFOs components. Nios II software is provided that demonstrates how to configure the SGDMA and create the necessary descriptor information used by the SGDMA. The design also demonstrates how to use the on-chip FIFO component to perform efficient clock domain crossing.

Design specifications

The design contains the following components:

  • Nios II processor
  • Two SGDMAs
  • Two on-chip FIFOs
  • Tri-state bridge
  • Phase-locked loop (PLL)
  • System ID

This design targets the Nios Cyclone® II and Stratix® II restriction of hazardous substances (RoHS) development boards. The Cyclone II design uses an 83-MHz control plane and a 200-MHz data plane. The Stratix II design uses a 100-MHz control plane and a 300-MHz data plane.

Figure 1. Scatter-Gather DMA Design Example


  1. S: Avalon memory-mapped slave port
  2. M: Avalon memory-mapped master Port
  3. SRC: Avalon streaming source port
  4. SNK: Avalon streaming sink port

Design functionality

The Nios II processor coordinates the design by performing the following steps in the order shown:

  1. Allocates memory to store the descriptors (transmit and receive pairs)
  2. Allocates memory to store the data that will be transferred (transmit and receive buffers)
  3. Creates incrementing test data in the transmit buffers and populates the descriptor pairs
  4. Writes the first descriptor pair to the SGDMAs, thereby starting the transfer
  5. Waits until both SGDMAs complete the transfer of all data buffers
  6. Validates that the received data matches what was transferred

All the descriptors and data buffers are stored in external SSRAM.

Each data buffer is transmitted through the system interconnect fabric via Avalon memory-mapped and Avalon streaming ports. The SGDMA fetches the data from SSRAM (Avalon memory-mapped port) and transmits the data to the on-chip FIFO component (Avalon streaming port). Avalon streaming ports provide flow control between source and sink pairs, allowing two on-chip FIFO components to transmit data between each other. The second SGDMA performs a similar transfer by reading the contents out of the on-chip FIFO component and sending the data to SSRAM to be later validated.

System Requirements

The system requirements to use the SGDMA design example include:

  • Quartus® II Software Version 7.1 or
  • Quartus II Software Version 8.0 or
  • Quartus II Software Version 8.1



You are free to use this design in any way you like. If you want to contibute to this project feel free to do so. I'm providing this design as is and Altera will not be supporting it.

Version history
Last update:
‎06-26-2019 11:49 PM
Updated by: