SOPC System Reset Considerations

[#1]

SOPC System Reset Considerations

Last Updated

August 18, 2009

Description

This paper discusses the issues that arise when implementing an FPGA design containing an SOPC Builder system with embedded PLLs. Much of the advice and observations in this paper can be applied to any FPGA design with PLLs, but the focus of this paper is on SOPC Builder systems which embed them. This paper only addresses the very typical PLL implementation which is a statically initialized PLL that is expected to run as configured for the entire runtime of the configuration. For applications which use the more advanced features of the PLLs like clock switchover and dynamic reconfiguration, some of the advice in this paper may still apply, however, these operational modes require more planning and implementation consideration than the scope of this paper will involve.

Contents

This paper is published in a PDF file along with a ZIP archive of source files for the example reset circuit discussed in the paper as well as a TAR archive of an example system that illustrates how one might deploy the circuit in an actual design.

• SOPC system reset considerations.pdf  - the paper
• source_files.zip - the source files for the reset circuit described in the paper
• 20090817_pll_monitor_example_3c120_90sp2.tgz - the project sources for the example system implementation of the reset circuit

Instructions

Downloading the pll_monitor example

Download the archive and place it in a directory on your system that does not include spaces in the path name. The entire path name of this directory must not contain spaces, so on Windows systems you should avoid putting these in the "My Documents" folder, or on your "Desktop" since these locations are subdirectories of the "Documents and Settings" path, and that would mean that these locations inherit the spaces in that part of the path name.

In order to extract the archives after downloading them, it is recommended that you run the "tar -xzf <filename>" command from a bash shell. For linux users you should have ready access to a bash shell. For windows users, you may need to install the Altera development tools to gain access to a bash shell. On Windows it is recommended that you install the Altera Quartus II FPGA development tools along with the IP base suite as well as the Nios II EDS development tools. Once these tool chains are properly installed on your workstation, you can launch a bash shell by running:

"Start -> Programs -> Altera -> Nios II EDS 9.0 -> Nios II 9.0 Command Shell"

Once you are in the bash shell, you can "cd" into the directory containing the archive that you downloaded, and run the following command to extract them:

tar -xzf <archive_filename>

Note that if you use some other archiving software to extract these archives, like WinZip, you may loose the execution privileges on some of the shell scripts within the archives that are used to perform various activities associated with building and using the example. If this happens, you can restore execute privileges from within a bash shell with the command "chmod +x <filename>". It is recommended that you avoid this situation by using "tar" to extract the archives from within a bash shell and avoid using any Windows oriented archive utilities with these archives.

Using the pll_monitor example

After you have extracted the archive you should be able to locate a "readme.txt" within the archive directory that will give you some guidance on how to get started with the project. The readme.txt should be right at the top level of the archive.

Requirements

The pll_monitor system design example is targeted for the 3C120 development board from Altera.